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Analog and Low-Power Digital

VLSI Design

July 7, 2015

LOW POWER VLSI DESIGN

Lecture 1
Introduction to Low-Power Design

July 7, 2015

Motivation
Historical Drivers of Low-Power Design
Microprocessor Scaling
Power Sources
Low-Power Design Methods

Analog and Low-Power Design


Lecture 1 (c) 2003

Motivation for Low-Power Design


Scaling of Si CMOS technology

Higher functionality with smaller chips


Higher performance at lower cost
Portability

Multi-media
Video display and capture
Audio reproduction & capture
Handwriting recognition
Notebook computer
Personal data assistant
Implantable medical electronics

New portable computer-intensive applications

Need for satisfactory battery life span


July 7, 2015

Analog and Low-Power Design


Lecture 1 (c) 2003

Historical Drivers of Low-Power


Design

Pocket calculators
Hearing aids
Implantable pacemakers and cardiac defibrilators
Portable military equipment for individual soldiers
Wristwatches
Wireless computing

July 7, 2015

Analog and Low-Power Design


Lecture 1 (c) 2003

Microprocessor Scaling Problems


Feature sizes of transistors keep shrinking
Magnitude of power/unit area keeps growing
Heat removal & cooling is worsening

Example: VDD 5 V

3.3 V

2.5 V

Power dissipation did not reduce plateaued at 30 W


Higher cooling costs for power densities of 50 W/cm2

Example: speech recognition needs a full PCB and

20 W of power to handle a 20,000 word vocabulary


NiCd batteries only provide 26 W / pound battery weight

July 7, 2015

Analog and Low-Power Design


Lecture 1 (c) 2003

Sources of Power Dissipation


Charging current
Due to logic transitions causing logic gates to charge/discharge
load capacitance

Short-circuit current
p-tree and n-tree momentarily shorted as logic gate changes
state

Leakage current

Diode leakages around transistors and n-wells


Increasing 20 times for each new fabrication technology
Went from insignificant to a dominating factor

July 7, 2015

Analog and Low-Power Design


Lecture 1 (c) 2003

Design for Low-Power Techniques

Reduced supply voltage

Charging power varies as VDD2


Reduce transistor threshold voltages to maintain noise margins
But reduced thresholds increase leakage currents exponentially

Change your CMOS logic family use a low-power one


Transistor resizing to speed-up circuit and reduce power
Use parallelism and pipelining in system architecture use
more, but slower, hardware
Standby modes clock disabling and power-down of selected
logic blocks
Adiabatic computing avoid gain/loss of heat during computing
Software redesign to lower power dissipation
July 7, 2015

Analog and Low-Power Design


Lecture 1 (c) 2003