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Roshan Sebastian VS
USN:1PI14LVS1412
INTRODUCTION:
STT-RAM is a new digital-data-recording technology,
which will lead to durable, high density memory chips impervious to
radiation and capable of virtually unlimited read/write cycles.
Called SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY
(STT-RAM) chips is cost competitive provide a
revolution in military and space electronics.
AIM:
To design a Memory chip that satisfies the following needs:
-Increase the Throughput of the system.
- Reliability and better Scalability.
- Must be resistive to radiation and Other hazards.
- Doubling of the number of transistors on a chip roughly every
two years- MOORES law.
Existing System
RAM
VOLATILE
Ex: SRAM,
DRAM.
NON-VOLATILE
Ex: MRAM,
PROBLEM STATEMENT
In conventional RAMs we are facing following problems:
Scalability problem (MRAM).
write disturbance under some conditions, which affects
accuracy and retention.
More current is needed.
An external magnetic field is necessary(MRAM).
More Voltage is required for the functionality of the chip.
The speed of writing is slow.
The Challenge
To design the universal memory chip that satisfies all the aims and
overcomes all the problems specified.
PROPOSED SOLUTION
Use SPIN TRANSFER TORQUE technique to design
the Non-Volatile RAM.
Tunnel
Magnetoresistance
(TMR)
4nm
1..2nm
3nm
3nm
SPIN TORQUE TRANSFER RAM
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M1 exerts torque on
incoming electron, that
become spin polarized in
M1 direction. This spin
polarized current in turn
exerts a torque on M2,
causing M2 precision and
switching.
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WORKING OF STT-RAM:
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MRAM
STT_RAM
External magnetic field is required for switching but this is not required
in case of STT-RAM.
SPIN TORQUE TRANSFER RAM
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WRITING PROCESS:
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NN STT-RAM CHIP.
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FABRICATION:
STT-RAM cell
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Optimization results
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Conclusion
It combines the speed of SRAM.
The non-volatility of flash memory.
Cost effective and low-power memory solution like DRAM.
No limit for write-read cycles (flash 100,000)
Radiation-resistant.
Greater Performance, reliability and Scalability.
All leads to STT-RAM being used as Universal memory
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References
1. X. Fong, S. H. Choday, and K. Roy, Failure Mitigation Techniques for 1T-1MTJ
Spin Transfer Torque MRAM Bit_cells,VLSI Systems vol.22,NO. 2, Feb. 2014
2. X. Fong, S. H. Choday, and K. Roy, Bit-cell level optimization for non-volatile
memories using magnetic tunnel junction and spin-transfer torque switching, I
EEE Trans. Nanotechnol., vol. 11, no. 1, pp. 172181, Jan. 2012
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Q/A
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THANK YOU
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