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SPIN TRANSFER TORQUE-RAM

SPIN TORQUE TRANSFER RAM

Roshan Sebastian VS
USN:1PI14LVS1412

INTRODUCTION:
STT-RAM is a new digital-data-recording technology,
which will lead to durable, high density memory chips impervious to
radiation and capable of virtually unlimited read/write cycles.
Called SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY
(STT-RAM) chips is cost competitive provide a
revolution in military and space electronics.

SPIN TORQUE TRANSFER RAM

AIM:
To design a Memory chip that satisfies the following needs:
-Increase the Throughput of the system.
- Reliability and better Scalability.
- Must be resistive to radiation and Other hazards.
- Doubling of the number of transistors on a chip roughly every
two years- MOORES law.

SPIN TORQUE TRANSFER RAM

Existing System
RAM

VOLATILE
Ex: SRAM,
DRAM.

SPIN TORQUE TRANSFER RAM

NON-VOLATILE
Ex: MRAM,

PROBLEM STATEMENT
In conventional RAMs we are facing following problems:
Scalability problem (MRAM).
write disturbance under some conditions, which affects
accuracy and retention.
More current is needed.
An external magnetic field is necessary(MRAM).
More Voltage is required for the functionality of the chip.
The speed of writing is slow.

SPIN TORQUE TRANSFER RAM

It has no capacity to preserve data under radiation and other


hazards.
The user needs to move data from one format to another,
because it does not have the ability to work with virtually all
systems equally well.
Power trade off problem- decrease in area of the chip
increases the power consumption.

SPIN TORQUE TRANSFER RAM

The Challenge

To design the universal memory chip that satisfies all the aims and
overcomes all the problems specified.

SPIN TORQUE TRANSFER RAM

PROPOSED SOLUTION
Use SPIN TRANSFER TORQUE technique to design
the Non-Volatile RAM.

STT-RAM is a new digital-data-recording technology,


which will lead to durable, high density memory chips impervious to
radiation and capable of virtually unlimited read/write cycles.

SPIN TORQUE TRANSFER RAM

Tunnel

Magnetoresistance
(TMR)

If the orientation of one of the magnetic


layers be changed then
the device will act as a filter, or spin
valve, letting through more
electrons when the spin orientations in the
two layers are the same
and fewer when orientations are oppositely
aligned

The electrical resistance of the device can


therefore be changed
dramatically.

4nm
1..2nm

Al2O3 (tunneling barrier)

3nm

CoFe (fixed layer)


Ru

3nm
SPIN TORQUE TRANSFER RAM

NiFe (free layer)

CoFe (pinned layer)


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The resistivity and magnetic field strength of MTJ during


logic 0 and logic 1.
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Spin Transfer Torque:


A spin-polarized current injected into a ferromagnetic layer can
induce a torque on its magnetization, hence rotate the
magnetization.

SPIN TORQUE TRANSFER RAM

M1 exerts torque on
incoming electron, that
become spin polarized in
M1 direction. This spin
polarized current in turn
exerts a torque on M2,
causing M2 precision and
switching.
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WORKING OF STT-RAM:

Change in magnetization direction by the application of direct current


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MRAM

STT_RAM

External magnetic field is required for switching but this is not required
in case of STT-RAM.
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The STT-RAM ARCHITECTURE:

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WRITING PROCESS:

Parallel magnetic effect in MTJ or logic 1 state


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Antiparallel magnetic effect in MTJ or logic 1 state


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SPIN TORQUE TRANSFER RAM

NN STT-RAM CHIP.

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FABRICATION:

First generation MRAM cell

SPIN TORQUE TRANSFER RAM

STT-RAM cell

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Failure mitigation techniques for 1T-1MTJ STT_RAM cell


Possible failures in 1T-1R STT-RAM cell
1.Write failure
2.Decision (read)failure
3.Disturb failure

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Four failure mitigation techniques


A. Word Line Voltage Boosting

Here gate voltage boosted to lower Tx resistance


and allow more current to flow through MTJ

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B.Transistor Body biasing

Here bit cell current increased without increasing width of


Tx by lowering threshold Vt

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C.Write Voltage Bossting

Here current increased by increasing bit line voltage


beyong Vdd

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D. Applied external magnetic field

Here magnetic field is applied to assist


free layer magnetization

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Optimization results

Word line voltage boosting achieved most reduction in


access transistor width and write power consumption
However read failure limited minimum width that
could be used
The applied external field was most energy efficient
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Conclusion
It combines the speed of SRAM.
The non-volatility of flash memory.
Cost effective and low-power memory solution like DRAM.
No limit for write-read cycles (flash 100,000)
Radiation-resistant.
Greater Performance, reliability and Scalability.
All leads to STT-RAM being used as Universal memory

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References
1. X. Fong, S. H. Choday, and K. Roy, Failure Mitigation Techniques for 1T-1MTJ
Spin Transfer Torque MRAM Bit_cells,VLSI Systems vol.22,NO. 2, Feb. 2014
2. X. Fong, S. H. Choday, and K. Roy, Bit-cell level optimization for non-volatile
memories using magnetic tunnel junction and spin-transfer torque switching, I
EEE Trans. Nanotechnol., vol. 11, no. 1, pp. 172181, Jan. 2012

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Q/A

SPIN TORQUE TRANSFER RAM

Questions and answer time

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SPIN TORQUE TRANSFER RAM

THANK YOU

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