You are on page 1of 77

Chapter 13

Memory Devices and

Memory Basics
• Memory is used to store data or
instructions for a microprocessor unit
(MPU) system.
• The stored data is organized in an array
of bits.
• Bits are stored in locations called

Memory Types
• RAM (random access or Read/Write
memory): Memory that can be written to or
read from in a random order (addresses).
• ROM (read only memory): Memory that can
only be read from in a random order.
• Sequential Memory: Memory that can be
written to or read from but only in a sequential
order (addresses).

Memory Register – 1 • Simplest memory element is a D-type flip-flop or latch. • An octal latch can be used to store a byte of data. 4 .

Memory Register – 2 • When WRITEn (EN) goes low.. then high. • When READ is set to a 1. • When READ = 0. 5 . the DATA_OUT lines are tristated. the data on DATA_IN [7.0] is latched into the register. the latch data output is enabled to DATA_OUT.

Memory Register – 2 6 .

Memory Register – 2 7 .

• Instantiated as megafunctions based on the LPM_LATCH. 8 . • 8-bit tristate output instance of the LPM_BUSTRI component.5 in textbook).Memory 4 x 8 (Write) – 1 • Uses four octal latches to store 4 bytes of data at different addresses (see Figure 13.

• The input data (to be written) is placed on dat_in[0:7] and the address of the byte on ADDR[0..1]. 9 ..1].Memory 4 x 8 (Write) – 2 • A 2-to-4 decoder is used to select the Latch (1 of 4) based on the address input on ADDR[0.

10 .Memory 4 x 8 (Write) – 3 • The WRITE signal is pulsed low to select 1 of the 4 bytes and write the data to that register. • None of the other registers has data written into them.

Memory 4 x 8 (Read) – 1 • Data from each latch is output to the inputs of an octal (8-bit) 4-to-1 multiplexer. 11 . • The address inputs are applied to the MUX select lines (ADDR[0.1]) to select 1 of the 4 data input bytes and transfer it to the MUX output..

12 . • If two or more were read simultaneously.Memory 4 x 8 (Read) – 2 • The data is then read by READ = 1 to enable the tristate drivers and place the byte on dataout. there would be bus contention. • Again the data from one and only one address is read at a time.

Memory 4 x 8 (Read) – 2 13 .

• Large memory devices use the designators K (kilobits = 1024 bits). or G (giga = 1073741824). 14 . M (mega = 1048576 bits).Memory Capacity • Memory size is specified by the address and data size such as 4 (addresses) x 8 (data). • A 4 x 8 memory block stores 32 bits or 4 bytes with 1 byte = 8 bits.

Address Lines – 1 • A memory device of 8K x 8 (8 kilobits) would require 13 address lines to address all locations in the device (213 = 8192 = 8 x 1024). the second byte is at = 0 0000 0000 0001. and so on with the last byte at address 8191 = 1 1111 1111 1111. 15 . • The address of the first byte (13 bits of data) is = 0 0000 0000 0000.

• All memory devices require address lines to point to a location in the memory array.Address Lines – 2 • A memory device covers a range of addresses such as 0000H to 1FFFH (given in HEX) for the 8K device. 16 .

Address Lines – 3 17 .

Address Lines – 4 18 .

• Memory devices also require some control lines to define the read or write processes. 19 . nibble.Memory Control Lines – 1 • Memory devices require data lines (depends on organization of arrays (bit. byte)) and address lines (depends on size of array).

• The CS/CE line is used to enable the memory to allow read or write data transfers. 20 .Memory Control Lines – 2 • All memory devices have one (or more) enable inputs such as chip enable (CE) or chip select (CS). (Usually Active Low ). the device cannot be accessed. CS / CE • When it is a 1.

• All memory devices have a read (G or OE) signal to allow data to be read FROM memory (if CS is active). 21 .Memory Control Lines – 3 • RAM memory devices have a write (W or WE) signal to allow data to be written TO memory (if CS is active). • Some SRAM devices have a R/W signal. does both.

Memory Control Lines – 3 22 .

Data is stored in a cell indefinitely until power is turned off. 23 .RAM Definitions – 1 • Volatile: A memory is volatile if its stored data is lost when electrical power is lost. • Static Ram (SRAM): Consists of arrays of memory cells that are flip-flops.

The data is stored as a charged or discharged state on the capacitor.RAM Definitions – 2 • Dynamic RAM (DRAM): Consists of arrays of memory cells that are capacitors. and then it needs to be refreshed. 24 . • The capacitor can only hold the charge for a short time (ms).

a DRAM Module = 1 GB (for gigabyte).SRAM/DRAM Comparison • DRAMs have larger memory capacity. A single DRAM = 256 MB. 25 . • DRAMs require refreshing and multiplexed addresses. • SRAMs have faster access times. • DRAMs consume less board area.

SRAM Memory Cell – 1 • Three basic SRAM cell technologies are bipolar. NMOS. • All three types use cross-coupled transistors to make up the basic flip-flop storage cell. and CMOS. 26 .

SRAM Memory Cell – 2 27 .

SRAM Memory Cell – 3 28 .

SRAM Memory Cell – 4 29 .

Q6.SRAM Memory Cell – 5 • In the basic NMOS cell. Q1 and Q2 are always biased to act as a Load Resistor for Q3 and Q4. • The Data from cell is then “passed” to the BIT Line and Line. BIT 30 . • The Data in a cell can be read by setting ROW_SELECT = 1 to turn on Pass Transistors Q5.

SRAM Memory Cell – 6 • To store a ‘0’. • Q3 is then ON to store the 0. place a 0 on the bit line and set ROW_SELECT = 1. Q6) to place a 0 to Q4 (it is off). • This turns on the Pass Transistors (Q5. • A ‘1’ can be stored in a similar fashion. 31 .

• The address buffer (enabled by CS  0 ) splits the address inputs (A0–A18) for the column and row decoders.SRAM Array Design – 1 • The cells are placed in a 512 row by 8192 column array. 32 .

SRAM Array Design – 2 33 .

• The data in or out is provided on the 8-bit data bus on the array. 34 .SRAM Array Design – 3 • Columns are divided into groups of 8 bits (for a 1-byte output) for each read or write operation.

• Adds more complexity to read/write cycles to allow refreshing. • Capacitor charge will “leak” and needs to be refreshed every 8 to 64 ms (depends on the size of the array).DRAM Cells – 1 • Basic cell is a MOS capacitor (to store charge) and a pass transistor. 35 .

DRAM Cells – 2 36 .

DRAM Cells – 3 • Memory cells have fewer components than a SRAM device. 37 . • This accounts for the higher densities possible than with SRAM.

• DRAMs use a multiplexed row and column address inputs to the array to save on pin count on the IC.DRAM Arrays – 1 • Most DRAM devices are bit organized (a single bidirectional data pin) instead of word (usually a group of 8 data pins) in SRAM. 38 .

DRAM Arrays – 2 • The multiplexed row and column address inputs must be demultiplexed to send to separate row and column decoders for the array. 39 . • Two negative edge trigger controls are used to latch addresses to the R/C buffers.

CAS (Column Address Strobe).CAS/RAS RAS (Row Address Strobe). 40 .



CAS/RAS Timing
• Refer to Figure 13.15 in the textbook.
• First the row address (usually lower
order address lines) are input and
loaded by the low pulse on RAS.
• Then the column addresses are input
and loaded by a low pulse on CAS.

ROM Basics
• ROM is nonvolatile memory and it is
used to store firmware such as a PC
operating system (the BIOS).
• Stores data that executes tasks that do
not change such as a “Bootstrap”
program for an MPU.

• MASK ROM now replaced by FLASH memory. because the data is stored permanently during the ROM manufacturing (or fabrication). 44 . • A logic 0 is stored by connecting the drain of the MOSFET to the column line.ROM Array – 1 • First type of ROM is called a MASK ROM.

ROM Array – 2 45 .

46 . it just floats to a 1. • The Row and Column Select Lines are used to read data through the Sense Amplifier.ROM Array – 3 • A logic 1 is stored as an open connection.

• The basic structure of the EPROM cell is based on the FAMOS FET. 47 .EPROM Basics • Erasable Programmable ROM: A ROM that can be programmed (“burned”) by the user and erased later by exposing it to UV light. • It is nonvolatile and reprogrammable.

48 .EPROM Programming – 1 • The FAMOS FET is a floating gate avalanche MOSFET Gate. • An unprogrammed FAMOS cell has a low threshold. so the transistor is turned ON to store a logic 1. • The cell is programmed by a high energy (12 V to 25 V) pulse on the row select to raise threshold for a logic 0.

• This sets all cells to the unprogrammed state (logic 1) by releasing electrons trapped in the floating gate. • Erasing is done by exposure to UV light for 20 to 45 minutes. 49 .EPROM Programming – 2 • The actual programming involves writing a logic 0 to cells and leaving the others unprogrammed (logic 1).

ramp. 50 .Applications • EPROMs can be used for logic tables and LUT for logic designs.18 in the textbook shows how to use an EPROM with a Digital-toAnalog Converter (DAC) to store waveform data such as sine. • Figure 13. or triangle.

• Similar in technology to the EPROM with the FAMOS Cell.EEPROM Basics – 1 • Electrically Erasable Programmable ROM: A type of ROM that can be reprogrammed and erased by a voltage (not UV) in the circuit. 51 .

52 . • The FAMOS FET used in the EEPROM uses a thin oxide layer to allow electrons to be driven out of the floating gate (electrically).EEPROM Basics – 2 • The FAMOS FET is reprogrammed by a Voltage Pulse on VPP.

EEPROM Basics – 2 53 .

• Smaller memory capacity than SRAM and DRAM.Comparison to SRAM • EEPROM has slower access times than SRAM. • EEPROM has a fixed number of write/erase cycles ( 100K ). 54 .

• Sector: A segment of the flash memory that forms the smallest unit that can be erased or programmed at one time.Flash ROM – 1 • Flash ROM: Non-volatile memory (similar to EEPROM) that can be programmed and erased in sectors rather than a byte at a time. 55 .

56 . • Bottom Boot Block: A boot block sector placed at the lowest address.Flash ROM – 2 • Boot Block: A sector in flash reserved for primary firmware. • Top Boot Block: A boot block sector placed at the highest address.

• Not all sectors are the same size. • One sector in a Flash ROM is reserved for PC Firmware called the Boot Block.Flash ROM – 3 • Flash ROM is usually larger than standard EEPROM (8 MB). 57 .

58 . S2 is 8 KB. the next sector S1 is 8 KB. • The sectors are shown as separate partitions and it uses Bottom Boot Block. • The Boot Block S0 (16 KB) is from 0000 to 3FFF.Flash ROM – 4 • An example 512K x 8 flash is shown in Figure 13. and S3 is 32 KB.20 in the textbook.

59 .Sequential Memory Basics – 1 • Sequential Memory: Memory in which the stored data locations can NOT be read from or written to in random order (must be in sequential locations).

such as a queue. such as a stack. 60 .Sequential Memory Basics – 2 • First In First Out (FIFO): A sequential memory in which the stored data is read out in the same order as it was stored. • Last In First Out (LIFO): A sequential memory in which the last data stored is the first data read.

Sequential Memory Basics – 3 61 .

Sequential Memory Basics – 4 62 .

• A special area in SRAM called the stack is reserved for program use. 63 .LIFO – 1 • The most common use of a LIFO is for stack memory in an MPU-based system.

• The stack pointer is initialized to the top of the stack.LIFO – 2 • A stack pointer is used to keep track of the stack memory address (location) currently in use (it increments or decrements). 64 .

65 .LIFO – 3 • As data values d. • As data values a. b. b. and a are stored on the stack the pointer decrements to the previous address. c. and d are read from the stack the pointer increments. c.

but MPU BUSSES are x32 or x64.DRAM Modules – 1 • Most DRAM ICs are x4 or x8. 66 . such as SIMM or DIMM modules. • DRAM ICs are combined on DRAM modules to expand the bus size to accommodate the MPU.

22 in the textbook shows a 64M x 32 memory module constructed of 4 64M x 8 DRAM ICs.DRAM Modules – 2 • Figure 13. 67 . • Uses a common CS to all 64M x 8 DRAM Devices and a 13 bit multiplexed address (A0–A13) for the 64 MB.

• Double I/O transfer rate for the using double data rate (DDR) SDRAM. • Fastest memory in transferring data to and from other components. 68 .SDRAM • Synchronous DRAM (SDRAM) data is synchronously transferred to and from the data bus by the clock.

• Reduces data transfer time. • Controls for ROW and COLUMN select carried on separate control busses. 69 . • Address pins multiplexed.Rambus Channel • Architecture uses a special bus layout. • Connects a number of DRAMs in a bus called a Rambus channel.

Memory Systems – 1 • Address Space: A block of continuous addresses in a memory system. 70 . • Memory Map: A diagram showing the total address spaces of a memory system and the placement of devices in that space.

71 . • The address decoder is used to generate individual CS for each device to avoid bus contention in the memory system.Memory Systems – 2 • Address Decoder: A digital combinational circuit that is used to enable specific memory devices by the address bus in a larger memory system.

Memory Systems – 3 72 .

Memory Systems – 4 73 .

7FFFH. • CS 0  A15 and CS 1  A15 74 . The next SRAM (32K x 8) is in space 8000H .FFFFH.Memory Systems – 5 • The first SRAM (32K x 8) is in address space 0000H .

BFFFH. The next SRAM (16K x 8) is in space 8000 .Example 13. • CS 0  A15  A14 and CS 1  A15  A14 75 .4 • The first SRAM (16K x 8) is in address space 0000H .3FFFH.

Example 13.4 76 .

4 77 .Example 13.