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D IG ITAL SYSTEM D ESIG N BEE3133

Group Member
•Tan Ming Horng
•Tan Nian Yee
•Muhamad Zulhilmi bin Mohamad Hamizi
•Aminuddin bin Aripin
•Norwahida bt Mustaffa

Introduction

• Traditional method may has some disadvantages like take more times to calculate and not efficient when it comes in large amount of members  Traditional measures are not hard to determine in real elections. • This system help to measure of residual vote rate become easier. faster and efficiently. but this does not include errors where the voter casts a vote for the .Introduction • Voting system is the way which done by a voter to make a choice between options and decision.

Problem Statem ent .

The chairman of senate. YES. who stays at podium. The system implement in VHDL code in and demonstrate by using FPGA development kit. . But in FPGA board. This is because the limitation on the board and the overload of voltage. we demonstrate for 4 senate members only. TIE OR NO. SW1 and SW2.Problem Statem ent  This system will be use in senate which consist of 200     members. The output is composed of three singles LED that indicate the result of vote. has one switch which uses to disable circuit when not use are. The SW2 are use to give the decision between YES or NO. Thera are three 7 segment LED display indicate the number of members voting. Each member will has two switches. The SW1 are used to check the number of the present member which means that the absent members can be detect.

Principles ofO peration .

Principles ofO peration CIRCUIT DIAGRAM .

Principles ofO peration SIMULATED CIRCUIT (PODIUM) senate adder substractor decoder 7-segment comparator decoder .

D iscussion .

. Each adder has two inputs and two outputs. To count the vote for 200 senators.  2. three 7 segment LED display indicate the number of members voting. we use 6 half adders to build it. Our VHDL code can support for 200 senators. we have to design a voting system for 200 senators. From the problem requirement. SW1 use to indicate the attendance while SW2 use to vote. but due to the limitation of the adder. TIE OR NO. SW1 and SW2. The chairman of senate. we have to use larger or many adders. To make 4 senators as the input. we only can make 4 senators as the input of the voting system. YES. In addition. has one switch which uses to disable circuit when not use are. Each senator has two switches. who stays at podium. The output is composed of three singles LED that indicate the result of vote.D iscussion  1.

. Disadvantages of circuit: High cost of adder.D iscussion 3. once exceed 200. The logic gates used can only support up to 200 senators. It is easy to modify. It is not limited only for 4 senators. 4. Adder used is fix and not changeable. Advantages of circuit: The circuit can support up to 200 senators. it will show error or ‘don’t care’ condition. Limitation of logic gates. The circuit is flexible and more organize. The six half adder used suppose can support 64 senators but we only support 4 senators due to lack of knowledge about the program used.

Conclusion .

Conclusion  Before we start a project. . 7 segments to display the number of vote counted and lastly master switch to enable and disable the circuit. We also use Quartus II software to simulate the system and FPGA development kit to produce the prototype of voting system. logic gate to detect the total numbers of vote available. 8 bit comparator to show the different between the Yes and No vote.  We used half adder to come the input. full adder to show the numbers of vote. decoder to convert the binary to decimal. we had to understand the problem requirement for our project that is electronic voting system.  We had successfully come out a systematic voting system by using VHDL code.

TH AN K YO U VERY M U CH .

LIN KS .

Principles ofO peration ADDER BASIC ADDER PODIUM .

Principles ofO peration BASIC ADDER PODIUM .

Principles ofO peration DECODER B decoder C PODIUM D .

Principles ofO peration 7-SEGMENT PODIUM .

Principles ofO peration COMPARATOR PODIUM .

Principles ofO peration SENATE PODIUM .

Subtractor FULL-ADDER PODIUM .

FU LL-AD D ER PODIUM .

Principles ofO peration 7-SEGMENT PODIUM .

Sm artArt .