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ELX 304 Electronic System Design

Part 1 Lesson 2
Design With Inputs

PowerPoint Slides
by Dr. Chow Li Sze

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Aims

Gained expertise in constructing state diagrams.

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D Flip-Flop

J-K Flip Flop

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S-R Flip Flop

T Flip Flop

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General Design with a single input

Step 1: Problem statement: Pattern Generator

steps.

If X=1, then a shortened pattern is produced, but the change can

only be initiated starting from the state whose output is 000.

A B C D E
F

A B C D E
F

6
steps
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A B E
F

A B E
F

4
steps
5

Step 2: State diagram

input

x
=

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In this example, there is one input (X), there will be 2 arrows

leaving each state.
In general, if there are n inputs, there will be 2n arrows leaving
each state.

Question:
If a state does not have any arrows leading to it, what is that
mean?
That state represents an initial condition.

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Step 3: State table

There are 2 next state for each present state

Notes: The State Table from Slide 8-13 doesnt match the corrected State
diagram in Slide 6 as in the UOS lecture notes. But they were used for
demonstration of the method.

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Step 4: Flip-flops
Step 5: State Assignment

There are 6 states, so we need 3 flip-flops.

Lets choose J-K flip-flops.
We cannot make the state assignments the same as the
outputs, because the outputs of different states are the same!
We can choose the following state assignment:

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A = 000
B = 001
C = 010
D = 011
E = 100
F = 101

Step 6: Excitation table

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Change Table

Step 6: Excitation table

Use the Change Table to fill up the Excitation Table:

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Step 7: Karnaugh Maps

inpu
t

J c = Kc = 1
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Step 7: Karnaugh Maps

We require output maps for Z1Z2Z3 which depends only on the
PRESENT STATE.

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Practice
Try it yourself for the Step 8: Circuit Diagram

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Example 2: Pattern Detector

Problem Statement:

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Design a synchronous circuit which will give a logic 1 for one

clock period when the following pattern is detected in a series
data stream .0 1 1 0
The final 0 can be the first 0 in the next pattern.
Use JK Flip-flops.
Typical sequence:

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State Diagram
Start at some known situation: the
input is 0 and so is the output
(State A).
If the input stays at 0, then there is
no reason not to stay at state A.
But if the input changes to 1, then
we want to remember this, so we go
to state B, and the output is still 0.
If we now get a second 1, then we go to state C.
C effectively is a memory that we have detected 0 1 1.
If we now get a 0 input, this is the sequence we want so we go to
state D which has an output 1.

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State Diagram
We now have to decide what happens
if the inputs dont follow the pattern we
want to detect.
In state B if we get a logic 0, we should
go back to A.
In state C if we get a logic 1, we have
to go to a new state E, because we
have now detected 3 logic 1s. We
then stay there until a logic 0 is
detected, when we go back to A, which
can be the start of a new sequence.

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State Assignment
Finally, when we are in state D, a logic
0 should take us back to A, but a logic
1 will take us to state B (because B is
remembering 01).

There are 5 states, so 3 Flip-flops and a 3-bit state assignment is

needed.
We will choose A = 000, B = 001, C = 010, D = 011 and E = 100,
labelling the Flip-flop outputs as Q1Q2Q3 respectively.

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Practice
Try it yourself to develop the:

State Table

Excitation Table

K-maps

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For a problem with 2 inputs, there will be 4 arrows leaving each

state!
Problem Statement:
A circuit has two inputs: X and Y.
The system must detect if both inputs are 0 or both inputs are 1
for three or more consecutive clock pulses.
The output must stay as logic 1 for as long as the sequence of
1s or 0 s is detected.
Use D Type Flip-flops.
Typical Sequence:

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State Diagram

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State Table

There are 7 states so we need 3 Flip-flops.

Since we have two inputs we shall need 5 variable K-maps!

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State Assignment

There is clearly some symmetry between states BCD and EFG, so

we should make their state assignments follow a similar pattern.

We shall try the following:

A = 000, B = 001, C = 010, D = 011,
E = 101, F = 110, G = 111

State 100 is not used, because we want to match the above pattern.

D type Flip-flops were chosen because that will make the Excitation
Table simpler (although the resulting logic is likely to be more
complex overall).

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Excitation Table
A

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B
A
E
A
C
A
E
A
D
A
E
A
D
A
E
A
B
A
F
A
B
A
G
A
B
A
G
A
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K-maps

The following 5 variable maps are each basically two 4-variable,

differing in the Q1 bit the left hand map is where Q1 = 0.
2
inputs

State 100 is not

used

XY

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K-maps

Note that the dont care entries have been chosen to generate
symmetrical functions.

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K-maps

symmetrical functions

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K-maps

State 100 is not

used

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Circuit
Diagram

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Unwanted State

In every case, we go back to an appropriate state.

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Summary
In this lesson, we have learned:

problems.

There is no definitive solution, but there is an optimum State

Diagram.
Notes: The choices we make may not be wrong, but they may not
be optimum. The optimum may not in fact be achievable in any
sensible time.

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Tutorial

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Tutorial Q.3
Design a circuit which will produce the following repeated three
output pattern under the control of two inputs X and Y as defined
below:

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Tutorial Q.4
Design a circuit which will detect the pattern .1011 in a serial
input. The final logic 1 in a detected pattern may form the first 1 in
the next pattern. When a pattern is detected the output must stay at
logic 1 for 2 clock periods.

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Tutorial Q.5
Design a circuit which will give an output if a 3 bit serial word
contains an odd number of logic 1s. The output is only 1 at the
end of the word. Assume that the words have been synchronised
externally, so that we start with the first bit of the word and not
halfway though a word.

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