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SDH MAPPING AND

MULTIPLEXING

Niranjan B

Generic Multiplexing Structure

9X4

9X3

TRANSPORT OF ASYNCHRONOUS
2048 KBPS TRIBUTARIES ON STM1
FRAME

TRANSPORT OF ASYNCHRONOUS 2048


KBPS TRIBUTARIES ON STM1 FRAME

Alternatives for Mapping 2048 Kbps


Tributary on STM1 Frame

Generic Multiplexing Structure

9X4

9X3

MUTIPLEXING PRINCIPLE
Container-n( n=1-4 ): A container is the information structure which forms the network
synchronous information payload for a virtual container

SIGNAL
2Mb

CONTAINER

MUX PRINCIPLE: CONTAINERS(C-n)

SIG
SIGNAL

C-12

SIGNAL
C-3

C-4

Asynchronous Mapping of 2048


Kbps Tributary into VC12

STRUCTURE OF C-12

R-

Fixed stuff bytes make up for the required number of bytes in the container.

C & C-

Jusification control bytes

S-

` Justification opportunity bit

Construction of C12

Fixed stuff bytes R make up for the required


number of bytes in the container.
They are introduced after every 32nd byte of
the tributary.
C and C bytes are the justification control
bytes.
S is justification opportunity byte.

The bit structures of C, C and S


bytes

C =

C1

C2

C =

C1

C2

S1

S =

S2

I=Information bit of the tributary

VIRTUAL CONTAINER: VC-n


Virtual Container-n(VC-n):It is the information structure used to support path layer
connections in the SDH.
Two types of VCs:

Lower order VC-n(n=1,2)


Higher order Vc-n(n=3,4)

P
O
H

CONTAINER

C-12 to

VC-12

C12 container into VC12 virtual container by adding the path overhead (POH) bytes.
The POH consists of a set of four bytes Vs, J2, Z6 and Z7, each of which is added sequentially before four C12 containers.

V5 Byte
Error detection, path
error status and signal
labeling .

B1-even parity bit for all the odd numbered bits of the previous VC12.
B2-even parity bit for all the even numbered bits of the previous VC12.
B3-error indication which is sent back towards path originator if more than one error is detected by the
parity bits.

B4- is Remote Failure Indication (RFI). It is set to 1 if path failure is declared.


B 5 to 7 provide signal label, e.g. 010 indicates asynchronous tributary in the container.
000 indicate unequipped VC12.

B 8 is path FERF (Far End Remote Failure) indication when TU12/TU2 path AIS or signal failure
condition is being received.

V5 Byte :
It provides for error detection, path error status and signal labeling

J2 Byte
J2 Byte

16Bytes

Repetitively transmit path access point identifier so that the


receiver can continuously identify the tributary.

Z6 Byte
For providing monitoring function in Tandem
Z7 Byte
For future use

MUX PRINCIPLE: TU-n/ AU


It is an information structure which provides adaptation between two
layers: -Between lower and higher order path layers for TU
-Between higher order path layer and section layer for AU

CONTAINER

POINTER is an indicator whose value defines the frame offset of a VC with


respect to the frame reference of the transport entity on which it is supported

Alignment from VC12- to TU-12

Formats of V1 and V2 bytes.


V1 &V2 bytes indicate location of V5
N- NDF- New Data Flag =1001 , whenever new TU-12 comes it is
inverted,
S- Trib type ,S=10 for TU12
IDID -10 bit offset of V5 bit from V2 byte

The four N bits are the New Data Flag


(NDF)
Their usual value is 1001.
When new alignment of VC12 is to be
given, these bits are inverted and new
pointer value is given in pointer bits.

The two S bits indicate the tributary unit


type. For TU12, S bits are 10.
The point value is a 0139 decimal number
coded in 10 bits which are placed in the last
two bits of V1 and 8 bits of V2 byte.
It is the offset of the V5 byte from the V2
byte.
V3 byte is used for negative justification
opportunity,.
V4 Byte :This byte is reserved

Pointer Generation
Usually the pointer value will remain unchanged
as indicated by NDF.
If due to some reason the pointer value needs
to be changed, the NDF bits are inverted and
the new value of the pointer takes effect.
If due to some reason the pointer value is to be
incremented by one byte or reduced by one
byte, positive or negative justification is
required.

Pointer Generation
For positive justification the I bits are
inverted.
The positive justification opportunity byte
which is next to V3 byte is filled with
dummy bits and in the next tributary unit,
the pointer value is incremented by one.
For negative justification, the D bits are
inverted and V3 byte is filled with one VC
12 byte. The subsequent pointer is
decremented by one in the next tributary
unit.

TU12 to TUG12
Multiplexing

TU12 to TUG2 Multiplexing

Tributary units (TU12) generated from three 2048


Kbps tributaries are multiplexed to form tributary unit
groups (TUG2)
TU12s of different tributaries are already in phase
synchronism. They are multiplexed byte by byte which
results in 12x9 matrix of TUG2
Note that first three bytes of TUG2 in the upper left
corner will contain the pointer bytes (V1, V2, V3, V4)
of the respective TU12s.
TUG2 contains 108 bytes and is transported either in
VC3 or VC4 container via TUG3

Generic Multiplexing Structure

Multiplexing of TUG2 into TUG3

VC12=9x4=36byte
TUG2=3x 9x
4=108byte
For transporting
TUG2 in VC4
containers,

Multiplexing of TUG2 into TUG3


As each TUG2 contains three 2048 Kbps
tributaries, 3x7x3 = 63 tributaries can be
transported by a VC4 container.

Multiplexing is done byte by byte.


TUG3 contains 86 columns.
The first two column contain fixed stuff and
3 bytes long null pointer indicator (NPI).
TUG3 can also contain VC3 in which case

NPI bytes contain the pointer for VC3.


First three bytes of TUG2 contain the TU12
pointer.
In TUG3, these pointer appear in the first row of
TUG3.
The first bytes of columns 3 to 23 of TUG3 contain
these pointers. (3pointers per TUG2 *7 nos of
TUG2=21)

Multiplexing of TUG3 into


VC4

Multiplexing of TUG3 into VC


4
Three TUG3 are multiplexed to form a VC4
container
The first column is POH.
The next two columns contain fixed stuff.
The rest of VC4 is formed by byte multiplexing of 3
TUG3s.
Note that all the pointer bytes of TU12 are available
in the first row in columns 10 to 72 of VC4.

Multiplexing of TUG3 into VC


4
6th byte of POH, called H4 byte is for the location of
pointer bytes of TU12 are fixed and known but it is
not known whether these bytes are V1 or V2 or V3 or
V4.
This is indicated by H4 byte of POH.
Thus, in a VC4 container, VC12 container can be
located by processing H4 and the pointer bytes of
TU12s.

H4 Byte
X XXXX X00

V1

X XXXX X0I

V2

X XXXX X10

V3

X XXXX XII

V4

Pointer Byte

Multiplexing of AU4 via AUG


.The

9 bytes at the beginning of row 4 are allocated to the AU4 pointer.

The remaining 9 rows by 261 columns is allocated to VC4.


The phase of VC4 is not fixed with respect to the AU4.
The location of the first byte of the VC4 with respect to the AU4 pointer is given
by pointer value.
The AU4 is directly placed into AUG. One AUG gives STM1.

Multiplexing of AU4 via AUG

STM N FRAME STRUCTURE

STM 0

STM 1

51840Kbps

155520Kbps

STM 4

STM 16

622080Kbps

24488320Kbps

Mapping of 2Mbps into STM N


2.048 Mbps

1 2 3

32
32 Bytes

(E1)

Stuffing Bytes

C-12

1 23

32
34 Bytes

POH (Lower Order)

VC-12

1 2 3

32
35 Bytes

Mapping of 2Mbps into STM N


Pointer

TU-12
36 Bytes

TU 12 is arranged

9 Rows

Into Matrix of 9 X 4

4 Columns

apping of 2Mbps into STM N


TU-12

TU-12

TU-12

9 Rows

4 Columns

4 Columns

4 Columns

Multiplexing

TUG-2

9 Rows

12 Columns

apping of 2Mbps into STM N


7 TUG-2s

Stuffing Bytes

X 7 TUG-2 TUG-3(multiplexing)

TUG 3

84 Columns
EAGLE PHOTONICS

86 Columns

Mapping of 2Mbps into STM N


TUG - 3

TUG - 3

TUG - 3
86 Columns

VC - 4
HOPOH

X 3 TUG3
Stuffing Bytes

258 Columns
261 Columns

Mapping of 2Mbps into STM N


VC - 4

Pay Load

POH

9 rows

261 Columns

AU Pointer

th Row

POH

AU 4 (Adding Pointer)

9 Columns

Pay Load

261 Columns

mapping E1.exe
EAGLE PHOTONICS

STM-1 frame structure

Mapping of VC12 into VC3


(2nd Alternate from E1 to VC-4)

Up to formation of TUG2, the process is


same.
From TUG2, directly VC3 is formed.
VC3 is further processed to form STM1
The pointer bytes of TU12 are present in
the first row of VC3
H4 byte of POH indicates whether the
pointer bytes are V1, V2, V3 or V4

Generic Multiplexing Structure

9X4

9X3

TUG-2 TO VC-3

Mapping of VC3/VC4 into STM1

Three VC3s or one VC4 can be


mapped into one STM1 frame.

TRANSPORT OF ASYNCHRONOUS 139264 KBPS


TRIBUTARIES ON STM1 FRAME
Mapping of Asynchronous 139264 Kbps into STM1

Generic Multiplexing Structure

9X4

9X3

TRANSPORT OF ASYNCHRONOUS
139264 KBPS TRIBUTARIES ON STM
1 FRAME
139264 Kbps stream is first organised into
C4 container of the size 9x260 (9 rows x
260cols).
By adding 1 column of path overheads to
this container yields VC4 which is of the
size 9x261 (9 rows x 261 columns).
VC4 is aligned into AU4.
AU4 is mapped into AUG.
One AUG gives STM1.

Mapping 139264 Kbps tributary into


VC4
Each of the 9 rows is partitioned into 20 blocks
consisting of 13 bytes each
In each row, one justification opportunity bit(s)
and five justification control bits (c) are
provided (Fig.3).
The first byte of each block consists of :
Either eight information bits (I), i.e. W bytes;
OR
One justification control bit (c) plus five fixed
stuff bits (R) plus two overhead bits (o), i..e x
byte; OR
Six information bits (I) plus one justification
opportunity bit(s) plus one fixed stuff bit (R),
i.e. Z byte.

Alignment of VC4 into AU4


VC4 is aligned into AU4, by means of AU4
pointer.

Multiplexing of AU4 via AUG


The 9 bytes at the beginning of row 4 are allocated to the AU4 pointer.
The remaining 9 rows by 261 columns is allocated to VC4.
The phase of VC4 is not fixed with respect to the AU4.
The location of the first byte of the VC4 with respect to the AU4
pointer is given by pointer value.
The AU4 is directly placed into AUG. One AUG gives STM1.

TRANSPORT OF ASYNCHRONOUS
34368 KBPS TRIBUTARIES ON STM1 FRAME

Asynchronous Mapping of 34368 Kbps Tributary into


VC3

One 34368 Kbps tributary can be mapped into a VC3, C3 container is formed first by
inserting justification and fixed staff bytes.
Justification makes the information bit stream and bytes synchronous to the SDH
environment .
In addition to the VC3 POH, the VC3 consists of a payload of 9x84 bytes every 125 ms.
This payload is divided in three subframes, each subframe consisting of :
1431 information bits (I);
two sets of five justification control bits (C1,C20;
two justification opportunity bits (S1,S2);
573 fixed stuff bits (R).

Construction of VC3 Container

VC3 Path Overhead Bytes


The VC3 path overhead is located in the first column of 9 row by 85 column
VC3 structure.
The POH consists of nine bytes denoted J1, B3, C2, G1, F2, H4, Z3, Z4, Z5

First Alternative
Mapping via AU3.

The three bytes at the beginning of row 4 are allocated to the


AU3 pointer, the remaining 9 rows by 87 column is allocated
to the VC3 and two columns of fixed stuff.
The byte in each row of the two columns of fixed stuff of each
AU3 shall be the same.
The phase of the VC3 and two columns of fixed stuff is not
fixed with respect to AU3.
The location of the first byte of VC3 with respect to AU3
pointer is given by the pointer value. As shown the three AU
3s are byte interleaved in the AUG. One AUG gives STM1.

Second Alternative
Mapping via AU4.
VC3 is first aligned into TU3. The TU3 consists of the VC3 with a 9 byte VC3 POH
and the TU3 pointer.
The first column of the 9 row by 86 column TUG3 is allocated to the TU3 pointer
bytes H1, H2, H3 and fixes stuff.
The phase of the VC3 with respect to TUG3 is indicated by the TU3 pointer. .

Multiplexing of three TUG3s into a VC4

Multiplexing on AU4 via AUG

The AU4 consists of the VC4 (Payload of 9 rows by 261 columns) plus 9 bytes at the beginning of row 4 (allocated to AU4 pointer).
The phase of VC4 is not fixed with respect to the AU4.
The location of the first byte of the VC4 with respect to the AU4 pointer is given by the pointer value. The AU4 is placed directly in the
AUG. One AUG gives STM1

Pointers
AUn Pointer

The AUn pointer provides a method of allowing flexible


and dynamic alignment of the VCn within the AUn frame

Dynamic alignment means that the VCn is allowed to


Float within the AUn frame.
Thus, the pointer is able to accommodate differences, not
only in the phases of the VCn and the SOH, but also in the
frame rates.

Synchronous Byte-interleaved
Multiplexing

4 parallel and frame synchronised STM-1 SDH signals may be


byte-interleave multiplexed together to form an STM-4 SDH
signal at 622.08 Mb/s (4x STM-1 bit rate). Byte-interleaved
multiplexing is accomplished by taking in turn, one byte from
each input tributary and placing it in the higher speed output
signal

Frame STM-16