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Computer Architecture

A Quantitative Approach, Fifth Edition

Chapter 1
Fundamentals of Quantitative
Design and Analysis

Copyright 2012, Elsevier Inc. All rights reserved.

Performance improvements:

Improvements in semiconductor technology

Introduction

Computer Technology
Feature size, clock speed

Improvements in computer architectures

Enabled by HLL compilers, UNIX

Compilers eliminate need for object code compatibility


UNIX became standardized and vendor-independent

Lead to RISC architectures

Instruction-Level Parallelism (ILP)


Optimized caches

Copyright 2012, Elsevier Inc. All rights reserved.

Performance improvements:

Introduction

Computer Technology
Together have enabled:

Lightweight computers
Productivity-based managed/interpreted
programming languages
Dominance of microprocessor-based computers

Copyright 2012, Elsevier Inc. All rights reserved.

Move to multi-processor

Introduction

Single Processor Performance

RISC

Tech-driven

Architecture/Org.-driven Power- and ILP-limited

Copyright 2012, Elsevier Inc. All rights reserved.

Cannot continue to leverage Instruction-Level


parallelism (ILP)

Introduction

Current Trends in Architecture


Pipelining, superscalar architectures
Unirocessor performance improvement ended in 2003

New models for performance:


Data-level parallelism (DLP)
Thread-level parallelism (TLP)
Request-level parallelism (RLP)

These require explicit restructuring of the


application

Copyright 2012, Elsevier Inc. All rights reserved.

Personal Mobile Device (PMD)

Desktop Computing

Emphasis on availability, scalability, throughput

Clusters / Warehouse Scale Computers

Emphasis on price-performance

Servers

e.g. start phones, tablet computers


Emphasis on energy efficiency and real-time

Classes of Computers

Classes of Computers

Used for Software as a Service (SaaS)


Emphasis on availability and price-performance
Sub-class: Supercomputers, emphasis: floating-point
performance and fast internal networks

Embedded Computers

Emphasis: price
Copyright 2012, Elsevier Inc. All rights reserved.

Classes of parallelism in applications:

Data-Level Parallelism (DLP)


Same operation applied to lots of data

Classes of Computers

Parallelism

Task-Level Parallelism (TLP)


Job can be separated into mostly independent tasks

Copyright 2012, Elsevier Inc. All rights reserved.

Classes of architectural parallelism:

Instruction-Level Parallelism (ILP)


Pipelining, superscalar, etc.

Classes of Computers

Parallelism

Vector architectures/Graphic Processor Units (GPUs)


Single instruction applied to multiple data

Thread-Level Parallelism
Independent, but tightly-coupled, execution
Can support frequent, fast interaction

Request-Level Parallelism
Independent, and loosely-coupled, execution
Supports less frequent interaction

Copyright 2012, Elsevier Inc. All rights reserved.

Single instruction stream, single data stream (SISD)

Single instruction stream, multiple data streams (SIMD)

Vector architectures
Multimedia extensions
Graphics processor units

Multiple instruction streams, single data stream (MISD)

The classic computer

Classes of Computers

Flynns Taxonomy

No commercial implementation

Multiple instruction streams, multiple data streams


(MIMD)

Tightly-coupled MIMD
Loosely-coupled MIMD
Copyright 2012, Elsevier Inc. All rights reserved.

Old view of computer architecture:

Instruction Set Architecture (ISA) design


i.e. decisions regarding:

registers, memory addressing, addressing modes,


instruction operands, available operations, control flow
instructions, instruction encoding

Defining Computer Architecture

Defining Computer Architecture

Real computer architecture:

Specific requirements of the target machine


Design to maximize performance within constraints:
cost, power, and availability
Includes ISA, microarchitecture, hardware

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Real computer architecture:

ISA
The programming interface presented

Microarchitecture (a.k.a. Organization)


The high-level design of the system
Implements the ISA
Ex: Intel Core i7 and AMD Opteron use different
microarchitectures to implement the x86 ISA

Defining Computer Architecture

Defining Computer Architecture

Hardware
The low-level design of the system
Detailed hardware design
Implements the microarchitecture
Copyright 2012, Elsevier Inc. All rights reserved.

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Integrated circuit technology

Transistor density: + 35%/year


Die size: + 10-20%/year
Integration overall: + 40-55%/year Moore's Law

DRAM capacity: + 25-40%/year (slowing)

Flash capacity: + 50-60%/year

Trends in Technology

Trends in Technology

15-20X cheaper/bit than DRAM


Limited lifetime

Magnetic disk technology: + 40%/year

15-25X cheaper/bit then Flash


300-500X cheaper/bit than DRAM
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Bandwidth or throughput

Total work done in a given time


10,000-25,000X improvement for processors
300-1200X improvement for memory and disks

Trends in Technology

Bandwidth and Latency

Latency or response time

Time between start and completion of an event


30-80X improvement for processors
6-8X improvement for memory and disks

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Trends in Technology

Bandwidth and Latency

Log-log plot of bandwidth and latency milestones


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Feature size
Minimum size of transistor or wire in x or y
dimension
10 microns in 1971 to 22nm in 2013
Transistor performance scales linearly
Integration density scales quadratically
Wire delay does not improve with feature size!

Trends in Technology

Transistors and Wires

Shorter wires, but resistance/length and


capacitance/length get worse
Tends to balance

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Problem: Get power in, get power out

Thermal Design Power (TDP)

Characterizes sustained power consumption


Used as target for power supply and cooling system
Lower than peak power, higher than average power
consumption

Clock rate can be reduced dynamically to limit


power consumption

Energy per task is often a better measurement


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Trends in Power and Energy

Power and Energy

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Dynamic energy

Dynamic power

Transistor switch from 0 -> 1 or 1 -> 0


Edyn proportional to x Capacitive load x V2

Trends in Power and Energy

Dynamic Energy and Power

Pdyn prop. to x Capacitive load x V2 x Freq. switched

Reducing clock rate reduces power, not energy

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Intel 80386
consumed ~ 2 W
3.3 GHz Intel
Core i7 consumes
130 W
Heat must be
dissipated from
1.5 x 1.5 cm chip
This is the limit of
what can be
cooled by air

Copyright 2012, Elsevier Inc. All rights reserved.

Trends in Power and Energy

Power

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Techniques for reducing power:

Do nothing well
Dynamic Voltage-Frequency Scaling
Low power state for DRAM, disks
Dynamic Overclocking
Hardware may boost speed until core heats
Turning off cores dynamically

Copyright 2012, Elsevier Inc. All rights reserved.

Trends in Power and Energy

Reducing Power

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Static power consumption

Currentstatic x Voltage
Flows even when device is cut-off
Scales with number of transistors
To reduce: power gating

Copyright 2012, Elsevier Inc. All rights reserved.

Trends in Power and Energy

Static Power

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Trends in Cost

Trends in Cost

Cost driven down by learning curve

Increased yield allows cost to be spread more

DRAM: price closely tracks cost

Microprocessors: price depends on


volume

10% less for each doubling of volume

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Integrated circuit

Bose-Einstein formula (an empirical model):

Trends in Cost

Integrated Circuit Cost

Defects per unit area = 0.016-0.057 defects per square cm (2010)


N = process-complexity factor = 11.5-15.5 (40 nm, 2010)
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Dependability

Dependability

Module reliability

Mean time to failure (MTTF)


Mean time to repair (MTTR)
Mean time between failures (MTBF) = MTTF + MTTR
Availability = MTTF / MTBF
Also, look at example on pp. 34-35

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End Lecture 1

Please read sections 1.1 1.8 (covered today)


We will cover remainder of chapter 1 next week
Homework?

Please check website for possible assignment

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