Professional Documents
Culture Documents
Outline
Use of Multiplexers/Selectors
Multi-point connections
A0
Sa
A1
B0
B1
MUX
MUX
Sum
Ss
DEMUX
S0
S1
A
0
1
Functional form
Logical form
Z
I0
I1
I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
Use
of
Multiplexers/Selectors
2:1
I0
Z = A' I 0 + A I 1
mux
I1
A
I0
I1
I2
I3
4:1
mux
A
I0
I1
I2
I3
8:1
mux
I4
I5
I6
I7
Alternative Implementation
A
I0
I1
I2
I3
Gate
GateLevel
Level
Implementation
Implementation
of
of4:1
4:1Mux
Mux
Transmission
TransmissionGate
Gate
Implementation
Implementationof
of
4:1
Mux
4:1 Mux
twenty transistors
0 4:1
1 mux
2
3S S
I4
I5
I6
I7
0 4:1
1 mux
2
3 S1 S0
8:1
mux
0 2:1
mux
1 S
I1
1 S
C
I2
I3
1 S
0
1
C
I4
I5
1 S
C
I6
I7
1 S
2
3 S0
S1
Multiplexers/Selectors as General
Purpose Blocks
n-1
0
1
2
3
4
5
6
7
8:1
MUX
S2 S1 S0
A
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
C
0
C
C
0
1
0
1
2
3
4:1
MUX
S1
A
S0
B
"Lookup Table"
Generalization of Multiplexer/Selector
Logic F
I I I
1
n-1 Mux
control variables
single Mux
data variable
0
1
0
0
0
1
1
0
1
1
Four possible
configurations
of the truth table rows
In
In
Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
K-map
Choose A,B,C
as control variables
Multiplexer
Implementation
TTL
TTLpackage
packageefficient
efficient
May
be
gate
inefficient
May C03
be gate
inefficient
ECE
Lecture
5
1
D
0
1
D
D
D
D
0
1
2
3
4
5
6
7
8:1
mux
S2
A
S1
B
S0
C
Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2
outputs
3:8 Decoder:
O0 = G S0 S1 S2
O1 = G S0 S1 S2
O2 = G S0 S1 S2
O1 = G S0 S1
O3 = G S0 S1 S2
O2 = G S0 S1
O4 = G S0 S1 S2
O3 = G S0 S1
O5 = G S0 S1 S2
O6 = G S0 S1 S2
10
Alternative Implementations
G
Output0
Select
/G
Select
Output0
Output1
Output1
/G
Select0
Output0
Output0
Output1
Output1
Output2
Output2
Output3
Output3
Select0
Select1
Select1
11
Select
G
Output
Select
Select
Output
0
Select
Select
"0"
Select
Output
1
Select
Select
Output
Select
Select
"0"
Select
12
Select
Output
"0"
"0"
S0 = 0, S1 = 0
Output
"0"
"0"
Output
"0"
"0"
Output
"0"
"0"
13
3:8
dec
S2
A
S1
B
S0
0
1
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
14
Enb
4:16
dec
S3 S2 S1 S0
A
B C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A BCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
F1
F2
F3
15
I7
I6
I5
I4
I3
I2
I1
I0
C
D
E
EN
I31 7 151
EN 1 6
5
1
Y5
I23 7 151
41 4
6
3
W 6
EN 1 5 52 2
1
3
5
1
I15 7 151
41 4
40Y 6
1
52 3
W
EN 1 6
5
2
3
3 1 Y 19
1
5C
7 151
41 4
B
4 0W 1 6A
6 5 3
0
22
5
9
1
3 1 Y 15 C
4
4 0 1 6B
13
W0 A
2
9
1
1 1 C
B
0 1A
S2 0
1
S1
S0
1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
1
5
Multiplexer Only
1 1G 1Y3
1391Y2
A 3 1B 1Y1
2 1A 1Y0
B
15 2G 2Y3
2Y2
13 2B 2Y1
14 2A 2Y0
153
YA 7 F(A, B, C, D, E)
B3
B2
YB 9
B1
B0
GBS1 SO
2 14
A B
7
6
5
4
9
10
11
12
7 EN 146
5
154
I31 7 151
1
3
6
7 EN
22
I5 145
31 Y 5
154
I23 7 I4151
40
3
7 EN 146 I3 1
W 6
2
I5 5 I2 2
9C
154 I1 3 1 Y 10
5B
I15 7 I4151
3 I0 4 0 W 116A
7 EN 146 I3 1
I5 5 I2 22 C 9 C
S2
154 I1 31Y 10
5B
I7 7 I4 151
S1
I6 6 I3 1 3 I0 40WD 116A
I5 5 I2 2 2 C 9C
S2E S0
5
I4 4 I1 3 1 Y 10
S1
D 11B
I3 3 I0 4 0 W
6A
I2 2 C 9 S2
S0
E
I1 1 10C
B
S1
D
I0 0 11A
C S2E S0
D S1
E S0
F(A, B, C, D, E)
Multiplexer + Decoder
16
5:32 Decoder
\EN
S4
S3
1G 1Y3
139 1Y2
1B 1Y1
1A 1Y0
2G 2Y3
2Y2
2B 2Y1
2A 2Y0
\EN
S2
S1
S0
\Y31
5:32
Decoder
Subsystem
.
.
.
S2
S1
S0
\Y0
S4 S3 S2 S1 S0
S2
S1
S0
S2
S1
S0
G1
G2A
G2B
Y7
Y6
Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A
\Y31
\Y30
\Y29
\Y28
\Y27
\Y26
\Y25
\Y24
Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y23
\Y22
\Y21
\Y20
\Y19
\Y18
\Y17
\Y16
Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
C
Y2
B
Y1
A
Y0
\Y15
\Y14
\Y13
\Y12
\Y11
\Y10
\Y9
\Y8
G1 Y7
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y7
\Y6
\Y5
\Y4
\Y3
\Y2
\Y1
\Y0
17
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V
n
2 -1
Dec
n-1
Address
Bit Lines
ECE
C03 Lecture
Internal
Organization
18
Address
ROM
8 w ords by
4 bits
A B C
address
F0
F1
F2
outputs
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
F3
0
0
0
1
1
0
1
0
Word Contents
F3
19
ROMs vs PLAs
Memory array
Not
Notunlike
unlikeaaPLA
PLA
structure
with
structure withaa
fully
fullydecoded
decoded
AND
ANDarray!
array!
Decoder
2n word
lines
n address
lines
2n words by
m bits
m output
lines
20
2764 EPROM
8K x 8
2764
VPP
PGM
A12
A11
A10
O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE
Read-Only Memories
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U3
OE
A13
/OE
A12:A0
D15:D8
D7:D0
+
16K x 16
Subsystem
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U1
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U2
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U0
OE
21
22
Clk
MUX
8 Product Term
AND-OR Array
+
Programmable
MUX's
AND
ARRAY
Output
MUX
pad
I/O Pin
Invert
Control
F/B
MUX
Programmable polarity
Seq. Logic
Block
Programmable feedback
23
Altera EPLDs
Altera EPLDs contain 8 to 48 independently programmed macrocells
Personalized by EPROM bits:
Global
CLK
1
Clk
MUX
Synchronous Mode
Flipflop controlled
by global clock signal
OE/Local CLK
Q
EPROM
Cell
Global
CLK
1
Clk
MUX
Asynchronous Mode
OE/Local CLK
Q
Flipflop controlled
by locally generated
clock signal
EPROM
Cell
Altera EPLDs
AND-OR structures are relatively limited
Cannot share signals/product terms among macrocells
Altera solution: Multiple Array Matrix (MAX)
Logic
Array
Blocks
(similar to
macrocells)
LAB A
LAB H
LAB B
LAB C
LAB D
LAB G
P
I
A
LAB F
Global Routing:
Programmable
Interconnect
Array
EPM5128:
8 Fixed Inputs
52 I/O Pins
8 LABs
16 Macrocells/LAB
32 Expanders/LAB
LAB E
25
Altera EPLDs
LAB Architecture
I/O Pad
Macrocell
ARRAY
I
N
P
U
T
S
I/O
Block
I/O Pad
P
I
A
Expander
Product
Term
ARRAY
Macrocell
P-Terms
Expander
P-Terms
26
Altera EPLDs
P22V10 PAL
INCREMENT
2904
0
0
FIRST
FUSE
NUMBERS
44
88
132
176
220
264
308
352
396
12
16
20
24
28
32
36
40
2948
2992
3036
3080
3124
3168
3212
3256
3300
3344
3388
3432
3476
3520
3564
3608
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
11
D
AR
SP
10
Q
00
01
23
5808
P
R
1
0
5809
OUTPUT
LOGIC
MACROCELL
3696
3740
3784
3828
3872
3916
3960
4004
4048
4092
4136
4180
4224
4268
22
P - 5810
R - 5811
924
17
P - 5820
R - 5821
4312
OUTPUT
LOGIC
MACROCELL
4356
4400
4444
4488
4532
4576
4620
4664
4708
4752
4796
4840
21
P - 5812
R - 5813
1496
OUTPUT
LOGIC
MACROCEL
L
16
P - 5822
R - 5823
8
4884
OUTPUT
LOGIC
MACROCELL
4928
4972
5016
5060
5104
5148
5192
5236
5280
5324
20
P - 5814
R - 5815
OUTPUT
LOGIC
MACROCEL
L
15
P - 5824
R - 5825
9
5368
2156
2200
2244
2288
2332
2376
2420
2464
2508
2552
2596
2640
2684
2728
2772
2816
2860
5
OUTPUT
LOGIC
MACROCEL
L
1540
1584
1628
1672
1716
1760
1804
1848
1892
1936
1980
2024
2068
2112
P - 5818
R - 5819
3652
968
1012
1056
1100
1144
1188
1232
1276
1320
1364
1408
1452
18
440
484
528
572
616
660
704
748
792
836
880
OUTPUT
LOGIC
MACROCEL
L
OUTPUT
LOGIC
MACROCELL
5412
5456
5500
5544
5588
5632
5676
5720
OUTPUT
LOGIC
MACROCEL
L
14
P - 5826
R - 5827
19
10
P - 5816
R - 5817
SYNCHRONOUS
PRESET
(TO ALL REGISTERS)
5764
11
INCREMEN
T
13
0
12
16
20
24
28
32
36
40
27
+
rows of interconnect
Anti-fuse Technology:
Program Once
Rows of programmable
logic building blocks
Wiring Tracks
S0
Basic Module is a
Modified 4:1 Multiplexer
S1
D0
2:1 MUX
D1
2:1 MUX
D2
2:1 MUX
D3
SOB
Example:
Implementation of S-R Latch
"0"
2:1 MUX
"0"
2:1 MUX
"1"
2:1 MUX
29
Actel Interconnect
Logic Module
Horizontal
Track
Anti-fuse
Vertical
Track
Interconnection Fabric
30
Input
Logic Module
Logic Module
Output
Input
31
IOB
CLB
IOB
CLB
IOB
Wiring Channels
CLB
IOB
IOB
IOB
IOB
CLB
32
TS
INV
OUTPUT
SOURCE
PASSIVE
PULLUP
Vcc
Enable
Output
PAD
MUX
Out
Output
Buffer
Direct In
Fast/Slow outputs
5 ns vs. 30 ns rise
SLEW
RATE
Registered In
TTL or CMOS
Input Buffer
R
Clocks
Global Reset
33
Reset
DIN
Any function of
5 Variables
Global Reset
A
B
C
D
E
Q1
D RD
Q
CE
Mux
Mux
Combinational
Function
Generator
Q2
G
Mux
Clock
Independent DIN
Mux
Mux
D RD
Q
CE
Clock
Enable
34
Q1
A
B
Mux
C Mux
D
E
Q2
Q1
C
D
E
F
Function
of 5
Variables
Mux
Mux
Function
of 4
Variables
Function
of 4
Variables
Mux
Q2
Q1
A
B
C
D
E
Mux
Mux
Mux
Q2
ECE C03
Mux
Mux
Function
of 4
Variables
D
Certain Limited
Functions of 6 Variables
E
F
Q2
Mux
Q1
A
B
Mux
Mux
Function
of 4
Variables
D
Q2
36
37
CLB
CLB
CLB
CLB
38
A2 B2
CLB
Cout
A1 B1
CLB
S3
CLB
S2
C2
A3 B3 A2 B2
CLB
A0 B0 Cin
C1
CLB
S1
C0
S0
A1 B1 A0 B0 Cin
S2
CLB
S0
S3
Cout
S1
C2
39
Direct
Connections
Direct Connections
Global Long Line
DI CE A
B
X
C CLB0
K
Y
E D R
Horizontal
Long Line
Switching
Matrix
Horizontal/Vertical
Long Lines
Switching Matrix
Connections
DI CE A
B
X
C CLB1
K
Y
E D R
Horizontal
Long Line
DI CE A
B
X
C CLB3
K
Y
E D R
DI CE A
B
X
C CLB2
K
Y
E D R
Vertical
Long Lines
Global
Long Line
40
Parameter
XC 2018
XC 4025
XC3195
Number of FFs
2560
1320
174
Number of I/ Os
256
176
74
no
no
41
Summary
42