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CACHE COHERENCY IN EMBEDDED SYSTEMS

PROBLEMS AND SOLUTIONS

CONTENTS
CACHE COHERENCY
HOW TO MAINTAIN CACHE COHERENCY
CACHE COHERENCE PROBLEM (DUAL CORE SYSTEM)
CACHE COHERENCE PROBLEM (MULTIPLE CPU SYSTEM)
SOLUTIONS TO CACHE COHERENCY PROBLEMS
SNOOPY CACHE-COHERENCE PROTOCOLS
SOLUTION FOR CACHE COHERENCE PROBLEM: SNOOPING
SOLUTION FOR CACHE COHERENCE PROBLEM : WRITE-THRU INVALIDATE
SOLUTION FOR CACHE COHERENCE PROBLEM : WRITE-BACK INVALIDATE
WRITE-THROUGH VS WRITE-BACK
MESI ALGORITHM
CACHE STATES IN MESI
SNOOP CONTROL UNIT (ARM ARCHITECTURE)
CACHE COHERENT INTERCONNECT (ARM ARCHITECTURE)
CONCLUSION
REFERENCES

CACHE COHERENCY
Cache coherency ensures that all processors or bus masters in the system
have the same view of memory.
Changes to data in the cache of one core are visible to other cores
If efficiently implemented, it would be impossible for cores to see stale
copies of the data.

HOW TO MAINTAIN CACHE COHERENCY


Disable Caching
Simplest mechanism, but costs significant core performance

Manage coherency through Software


Will take CPU cycles, bus bandwidth and power.
Performance degraded.

Manage coherency through Hardware


Most Efficient Solution

CACHE COHERENCE PROBLEM (DUAL CORE SYSTEM)

Load A
Store A<= 1

P0

P1

01

Memory

Load A
Load A

CACHE COHERENCE PROBLEM (MULTIPLE CPU SYSTEM)


P2

P1
u=?
$

P3
3

u=?

u :5 u = 7

u :5

I/O devices

u :5
Memory

SOLUTIONS TO CACHE COHERENCY PROBLEMS


SNOOPING

Enables all cache controllers to observe (or snoop) the activities of all other
processors and take appropriate actions to prevent the processor from obtaining
stale data.
Snooping protocol is further classified into 2 schemes:

Write-Thru Invalidate Scheme


Write-Back Invalidate Scheme

MESI Algorithm (Modified, Exclusive, Shared, Invalid)

SNOOPY CACHE-COHERENCE PROTOCOLS


State
Tag
Data

P1

Pn

Bus snoop

Mem

I/O devices

1. Bus: Everybody can listen to bus traffic


2. Each cache is snooping on the bus
3. Matches the address on the bus with its address
4. Most commonly used

Cache-memory
transaction

SOLUTION FOR CACHE COHERENCE PROBLEM: SNOOPING

Load A
Store A<= 1

P0

P1

0
1

Memory

0
1

Load A
Load A

SOLUTION FOR CACHE COHERENCE PROBLEM : WRITE-THRU


INVALIDATE
P2

P1
u=?
$

P3
u=?

u :5 u = 7

u :5

I/O devices

u :5
uMemory
=7

SOLUTION FOR CACHE COHERENCE PROBLEM : WRITE-BACK


INVALIDATE
P1

S
I

P2

75

P3

Memory

M
S

5
7

I/O devices

u: 5 7
Processor Action

State P1

1. P1 reads u
2. P3 reads u
3. P3 writes u
4. P1 reads u
5. P2 reads u

S
S
I
S
S

State P2

State P3
S
M
S
S

Bus Action
BusRd
BusRd
BusRdX
BusRd, Flush
BusRd

Data from
Memory
Memory
Memory
P3 cache
Memory

WRITE-THROUGH VS WRITE-BACK
Write-through protocol is simple
every write is observable
Every write goes on the bus
Only one write can take place at a time in any processor
Uses a lot of bandwidth!
Performance takes a hit in Write-Through

MESI ALGORITHM

Modified (M) Cache line has been modified. It is different from main
memory, and is the only cached copy.
Exclusive (E) Cache line is the same as main memory and is the only
cached copy.
Shared (S) Same as main memory but copies might exist in other caches.
Invalid (I) Line data is not valid as in simple cache.

CACHE STATES IN MESI

CACHE STATES IN MESI (Cont)

SNOOP CONTROL UNIT (ARM ARCHITECTURE)

CACHE COHERENT INTERCONNECT (ARM ARCHITECTURE)

CONCLUSION
Almost all modern day Smartphones are based on Octa-Core CPU Designs running at ultra high clock
frequencies. You cant even imagine the enormous amount of data processed by your Smartphone. This
data can be both secure and non-secure. Hence, maintaining the data integrity is of Utter importance for
any organization today. Since most of the data handled by the CPUs is in the Caches which are shared
by other CPUs, hence a Highly Efficient HW solution is required for maintaining the data coherency
among the caches.
WriteBack Invalidate Snooping scheme is the best among all Coherency schemes because it results in
High CPU performance along with reliable Cache coherency.

REFERENCES
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0425/ch03s12s01.html
https://en.wikipedia.org/wiki/Cache_coherence
https://en.wikipedia.org/wiki/MESI_protocol
http://meseec.ce.rit.edu/551-projects/fall2010/1-3.pdf
https://parasol.tamu.edu/~rwerger/Courses/654/cachecoherence1.pdf

THANK YOU !!!