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# Lecture 5

Combination Logic
Design
pom@ku.ac.th
Department of Computer Engineering
Kasetsart University

Acknowledgement
This

## lecture note has been summarized from

lecture note on Introduction to VLSI Design,
VLSI Circuit Design all over the world. I cant
remember where those slide come from.
However, Id like to thank all professors who
create such a good work on those lecture
notes. Without those lectures, this slide cant
be finished.

Topics
Combinational

logic functions.
Static complementary logic gate structures.

Combinational

## logic: function value is a

combination of function arguments.
A logic gate implements a particular logic
function.
Both specification (logic equations) and
implementation (logic gate networks) are
written in Boolean logic.

Gate design
Why designing gates for logic functions is nontrivial:
may

## not have logic gates in the libray for all logic

expressions;
a logic expression may map into gates that
consume a lot of area, delay, or power.

Function:

f = ab + ab
a

## is a variable; a and a are literals.

ab is a term.
A function is irredundant if no literal can be
removed without changing its truth value.

Irredundancy
A

## logical expression is irredundant if no literal

can be removed from the expression without
changings its value
Redundant

expressions:

a*b+a
a*b+a*b'
Irredundant

expressions:

a*b'+a'*b
a+c*d'

Completeness
A

## set of logical functions is complete iif we

can generate every possible Boolean function
using that set
The

## set { AND, OR, NOT } is complete

The set { NAND } is complete
The set { AND, OR } is not complete
Transmission gates are not complete.
If

## your set of logic gates is not complete, you

cant design arbitrary logic.
8

Minimality
A

## logic expression is minimal if no equivalent

form has a higher cost (i.e., literal count)
Minimality Irredundancy
CAD tools are available to find the minimal
(or near-minimal) form for:
Two

## level logic (AND/OR Sum of Products)

Multilevel Logic (Arbitrary network of gates)

Complementary:

## have complementary pullup

(p-type) and pulldown (n-type) networks.
Static: do not rely on stored charge.
Simple, effective, reliable; hence ubiquitous.

10

## Static complementary gate

structure
Pullup Network - drives output to VDD
Pulldown Network - drives output to GND

VDD

VDD

Pullup
Network
(p-transistors)
Inputs

Out
Pulldown
Network
(n-transistors)

Gnd

In

Out

Gnd
Inverter

11

Inverter layout
VDD
+

tub ties
out transistors
a

out

(tubs not
shown)

GND
12

## Pullup, pulldown networks

should NEVER conduct at
same time!
Pullup, pulldown networks are
duals
A
Parallel in pulldown implies
serial in pullup
Serial in pulldown implies
parallel in pullup
Gate Types:
Simple: NAND, NOR,
inverter
B
And-Or-Invert (AOI)
Or-And-Invert (OAI)

B
C
OUT = (A*(B+C))
A

13

Layout Considerations
Metal

## lines required for Vdd!, Gnd!

ndiff, pdiff must be separated by 10 lambda
Transistor options:
horizontal

Increased

## width implies increased driving capabilitiy,

but
Do the analysis first to see if its necessary

14

Interconnect

necessary):
Metal

1
Metal 2
Poly
Diffusion
Specify

## a well depending on process type

Use substrate contacts to prevent latchup

15

NAND gate
+

out
b

16

NAND layout
VDD
+
out
b

out tub
ties
b
a
GND
17

## Compare to Fig 3-10, p.

122
Differences from Magic
Explicit contact cuts
P-tub as well as N-tub
Larger N-well
Note transistor sizes
Note substrate contacts

18

NOR gate

+
b
a
out

19

NOR layout

VDD

a
out

tub ties
b
out
a

GND
20

## Compare to Fig 3-12, p.

123
Differences from Magic
Explicit contact cuts
P-tub as well as N-tub
Larger N-well
Note transistor sizes
Note substrate contacts

21

Transistors

## Divide into multiple transistors

Tie together sources, drains
Compare to Fig 3-9, p. 121
Missing but still needed:
substrate contacts

22

AOI/OAI gates
AOI

## = and/or/invert; OAI = or/and/invert.

Implement larger functions.
Pullup and pulldown networks are compact:
smaller area, higher speed than NAND/NOR
network equivalents.
AOI312: and 3 inputs, and 1 input (dummy),
and 2 inputs; or together these terms; then
invert.

23

AOI example
out = [ab+c]:
invert

symbol

circuit
or

and

24

Pullup

## and pulldown networks are duals.

To design one gate, first design one network,
then compute dual to get other network.
Example: design network which pulls down
when output should be 0, then find dual to get
pullup network.

25

## Dual network construction

b
b

dummy

dummy
26

Inverter - DC Analysis
A
NMOS off
PMOS lin

B
NMOS sat
PMOS lin

Vou t

NMOS sat C
PMOS sat

out

in

NMOS lin
PMOS sat

NMOS lin
PMOS off E
Vin

27

A

Vout VDD

## Vout Vin Vtp

Vout

D
E

2
Vtp VDD n Vin v tn
Vin Vtp 2 2 Vin VDD

2
p

VDD
2

## Vout Vin Vtn

2
2 p
V

V
in tn Vin VDD v tp
n

Vout 0

Note dependence on n/ p
' Wp
Recall: k' Wn
p kp
n

Ln

Lp

Source: N. Weste & K. Eshraghian, Principles of CMOS VLSI Design Addison Wesley, 1992

28

Logic

voltages
Logic

Logic

Static

VOL

29

## Examine DC Input/Output Curve (Fig 3-15, p. 120)

Pick points where slope = -1 as VIL , VIH

## Rationale: compare change in VIN , VOUT

VIN < VIL small change in VIN causes small change in VOUT
VIN > VOUT small change in VIN causes small change in VOUT

VIN < VIL < VIH small change in VIN causes large change in VOUT

30

"1"

OH
V
IH

V(y)
Slope = -1

V
OH

Undefined
Region

"0"

V
IL
V
OL

Slope = -1
VOL
V

IL

IH

V(x)

31

Noise Margin
A

Logic

Logic

Important

Definition:

## small random variations in voltage

Dont want noise to affect circuit output

32

Margin

## Changing beta (size)

ratio changes VIH, VIL

To balance noise
margin:

good enough

n
10
p
n
0.1
p

n
1
p

Vin

33

Gate Delay
Consider

## an inverter with "step function" input

Delay related to time to discharge / charge
CL
in
t

RL
CL

34

Simplifying Assumptions
Assume

## transistors turn on/off

instantaneously
Model transistor as a switch, resistor in series
Resistor

Vds
(See

## Fig. 2-6, p. 45 Fig 3-17, p. 123, Fig. 3-18, p.

123)
Use average of Vds/Id at:
middle

maximum

35

## Delay Calculation - Finding Rn

Vsat Vlin
Rn

/ 2
I sat I lin

EQ 3 1

Vsat V DD VSS

I sat

1 W
2
k V DD VSS Vt
2 L

Vlin V DD VSS Vt / 2
W 1
2
1 VDD VSS Vt
Ilin k VDD VSS Vt

L 2
2
2

2

3 W
2
k V DD VSS Vt
8
L
36

V
V
Rn sat lin / 2
I sat I lin

VDD V SS
VDD VSS Vt / 2

/ 2
1 W
3 W
2
2
k VDD VSS Vt
k VDD VSS Vt
2

L
8 L

5 V 5 V 2 V
L 3 DD 3 SS 3 t
Rn
2
W k' VDD VSS Vt

Rn = 3.9k
Rp = 14k

37

Equivalent

## Network - see p. 125

Eq. 3-6: voltage vs. time
Eq. 3-7: solve for 90%-10% time
single inverter: p. 106

38

Capacitor

## initially charged at VDD

Transistor approx. Rn
Fall time (90%-10%): tf = 2.2 * Rn * CL
V OUT
Rn

CL

39

Capacitor

## initially discharged (at Vss)

Transistor approx. Rp
Fall time (90%-10%): tp = 2.2 * Rp * CL
Rp
V OUT
CL

40

## Gate Delay Accuracy

Comparison

to Spice simulation:
Fig 3-19, p. 127
Estimate

## seems overly conservative, BUT

Step functions don't occur in "real life"
Spice

Fig. 3-20, p. 128
First

## inverter output a more realistic waveform

Second inverter delay comparable to estimate

41

## Gate Delay of NAND Gate

Pulldown:

series n-transistors
tf = 2.2 * (2 * Rn) * CL

Pullup:

parallel p-transistors
(worst case when one on)
tr = 2.2 * Rp * CL
V OUT
Rn

CL

Rn

42

## Gate Delay of NOR Gate

Pulldown:

parallel n-transistors
(worst case when one on)
tf = 2.2 * Rn * CL

Pullup:

series p-transistors
tr = 2.2 * (2 * Rp) * CL Rp

NOR

(why?)

V OUT
CL

43

Gate Delay
Consider

## an inverter with a rising input

Delay related to time to discharge / charge CL

VIN

VOUT

RL
CL

44

## Gate Delay - Definitions

Vin

50%

50%

tpHL

Vout

tpLH
90%
50%
10%

50%

tf
tr
Delay: time to reach 50% of final value
tpHL (book calls this td)
tpLH
Transition Time: time between 10% and 90%:
tf - fall time
tr - rise time
45

Simplifying Assumptions
Assume

## Step Function input

Model transistor as switch and resistor
Resistor

values of Vds

Use

middle

maximum

CL

Vss)
Book

Rp

Rn

46

## Delay Calculation - Finding Rn

Vsat Vlin
R n

/2
Isat Ilin
Vsat VDD VSS

EQ 31

1 ' W
2
Isat k n VDD VSS Vt
2 L
Vlin VDD VSS Vt /2
2

W 1
V Vt
2 1 V
Ilin kn VDD VSS Vt DD SS

L 2
2
2
3 W
2
kn VDD VSS Vt
8 L
47

## Delay Calculation - Finding Rn

Vsat Vlin
R n

/2
Isat Ilin

VDD VSS Vt /2
VDD VSS

/2

1 W
3 W
2
2
kn VDD VSS Vt
kn VDD VSS Vt
2 L

8 L
5
5
2
V V V
L 3 DD 3 SS 3 t
R n

W kn VDD VSS Vt 2

48

Vsat Vlin
R p

/2
Isat Ilin

EQ 31

## Vsat VSS VDD

1 W
2
Isat kp VSS VDD Vt
2 L

## Vlin VSS VDD Vt /2

2
W 1
2 1 VSS VDD Vt
Ilin kp VSS VDD Vt

L 2
2
2
3 W
2

kp VSS VDD Vt
8 L
49

## Delay Calculation - Finding Rp

Vsat Vlin
R p

/2
Isat Ilin

VSS VDD Vt /2
VSS VDD

/2

1 W
3 W
2
2
k VSS VDD Vt k VSS VDD Vt
2 L

8 L

5
5
2
V V V
L 3 SS 3 DD 3 t
R p
2
W k' VSS VDD Vt

50

## Summary: Calculating Rn and Rp

Assume

VSS=0 to simplify:

5
2
V V
L 3 DD 3 t
R n

W kn VDD Vt 2

2
VDD Vt
L
3
3
R p

W kp VDD Vt 2

51

Example: Calculating Rn
Use

## values from book:

VDD 5V Vt 0.7V

kn 73A/V2 L 2 W 3

5
2
VDD Vt

L
3
R n 3

W kV V 2
n DD t

2
(5V) (0.7V)

2
3
3
14K
2
3 kn 5V 0.7V

52

Example: Calculating Rp
Use

## VDD 5V Vt 0.8V kp 21A/V2 L 2 W 3

5

2
VDD Vt

L
3
3
R p
2

W kp V
DD Vt

5
2
(5V) (0.8V)

2
3
3

14K
2
2
3 (21A/V )5V (0.8V)

53

## Summary: Rn and Rp for

Minimum-Sized Transistors

type
Rn
Rp

VDD=5V

VDD=3.3V

3.9K
14K

6.8K
25K

54

## Inverter Delay with the model

Rising Input / Falling Output
Vout (t) VDDe

t
(R n R L )C L

EQ 3 6

Rp

V DD

t pHL

0.5VDD VDDe

(R n R L )C L

RL

EQ 3 7 *
t 90%

t 10%

CL

## t pHL (R n R L )CL ln(0.5) 0.69(R n R L )CL EQ 3 8

0.1
t f t10% t 90% (R n R L )ln
2.2(R n R L )CL EQ 3 9
0.9

Rn

55

## Inverter Delay with the model

Falling Input / Rising Output
t

## Vout (t) 1 VDDe (R n R L )CL

t pHL

(R
R
)C
0.5VDD VDD 1 e n L L

Rp

V DD

RL

t 10%

t 90%

CL

## t pHL (R n R L )CL ln(0.5) 0.69(R n R L )CL EQ 3 8

0.1
t r t 90% t10% (R n R L )ln
2.2(R n R L )CL EQ 3 9
0.9

Rn

56

Model
Fall

## time: n-transistors in series

tf = 2*2.2(Rn+RL)CL

Rp

Rp

RL

Rise

time: 1 p-transistor on
(for worst case)
tf = 2*2.2(Rn+RL)CL

CL

Rn

Rn

57

Fall

## time: one n-transistor on

(worst case)

Rp

tf = 2.2(Rn+RL)CL
Rp

Rise

## time: p-transistor in series

tf = 2*2.2(Rn+RL)CL
Rn

Rn

58

## Fall time: 2 n-transistors in series

(worst case)
tf = 2*2.2(Rn+RL)CL

B
A
C

## Rise time: 3 p-transistors in series

(worst case)
tf = 3*2.2(Rn+RL)CL

RL
CL

A
D
B

59

Approaches

## Current source model - treat transistor as current source

in saturation

tf

CL (VDD VSS )
CL (VDD VSS )

(EQ 310)
2
Id
0.5kn W /LVDD VSS Vt

tr

CL (VDD VSS )
CL (VDD VSS )

2
Id
0.5kp W /LVSS VDD Vt

Fitted model
Measure several circuit characteristics & fit to formula

Circuit Simulation - Most accurate approach

60

Accuracy of methods
Comparison

## to Spice simulation: Fig 3-20, p.

133

Model
Current Source Model
What
Use

to do:
simple models for

Quick

prediction of delay
Insight into circuit operation
Comparison of different circuits
Use

61

## Estimate tr and tf for a minimum-size inverter driving the

inputs of four minimum-size inverters
C INV

IN

OUT

C INV

C gp

CL
C INV

C gn

C INV

62

Estimate
Cgp=

0.3375fF

C =
gn

C gp

0.3375fF

CINV=

CL=

C INV
C gn

0.675fF

63

Now
t r=

23.61ps

t f=

83.61ps

64

Gate
Use

Rise

time tr:

## Worst case: 2 transistors

tr= 2.2 (2 Rp) C L
2.2 (2 14K) 50 10
3.08ns

15

in series
A

B
C

C L=50fF

Fall

time t :

B
tf= 2.2 (2 f R n ) C L
15
Worst
series
connection
2.2 case:
(2 3.9K)
50 10
F

0.86ns

65

Width
Increase

## width of transistor to:

Increase

current
Reduce effective resistance (R n or Rp)
Side-effect:

## increased input capacitance

5
2
V V
L 3 DD 3 t
3
R n(WNEW)

R n(W3)

2
WNEW kn VDD Vt WNEW

3
R p(WNEW)
R p(W3)
WNEW
66

## Example: Gate Delay of a NOR

(VDD=5V)
R n( W8)

R n( W3)
3.9k

R p(W 31)

3
1.46k
8

R n( W3)
14k

3
8

W=31
L=2

3
31

3
1.35k
31

OUT
A

W=8
L=2

C L=20fF

t f 2.2 R
n(W 8) C L
2.2 1.46k 20fF 0.064ns
t f 2.2 (2 R p( W31) ) C L
2.2 2 1.35k 20fF 0.12ns
67

Size
Rp

## the transistors in an inverter so that tr=tf

/ Rn = 13K / 3.9K = 3.47

Make

Wp approximately 3.5*Wn
W=10
L=2
VIN

VOUT

W=3
L=2

68

## Size the transistors in an AOI gate

so that tr=tf
Rp / Rn = 13K / 3.9K = 3.47
A
18
(round down to 3)
Size each worst case path for equal delay
Assume L=2 in all transistors
D

B
C

36

18
A

36

3
B 6

C 6

69

Delay

## Consider n-transistors in series:

T1 has higher Vt while C1 charged

## T1 turns on more slowly

CL discharges more slowly

## Delay (fall time) increases!

What to do?
Attempt to reduce parasitic
C1-internal node capacitance

## Place earliest-arriving gate inputs

near Gnd (VDD, for p-transistors)

To Pullup Network
OUT

T1

T2

CL

C1

+
V C1 =V sb1
-

V sb2 =0V

near output

70

Body Effect

Increasing Vsb

## increases width of depletion layer

raises the threshold voltage Vt
Vt n s Vsb s

## Example (p. 56): if Vsb=5V, Vt=0.16V (24% of Vt)

71

Power Consumption

## Static power consumption - due to leakage current

Diode leakage - reverse-biased diode junction
i o i s (e qV / kT 1)

W Vgs Vt / nVth
I sub I D0 ( )e
1
L

## Dynamic power consumption

Power consumed as outputs switch to
72

Charging

Capacitor

Current,

Energy: Eq. 3-10
Discharging

Capacitor

Current,

Energy: Eq. 3-13

73

Power:

## Energy per unit time

P = f*CL*(VDD-VSS)2 = f*CL*VDD2
Where
f

## = rate of change of gate output

Worst case: f=fclock (more likely f < fclock but f fclock
)
P depends only on f, CL, and VDD!
For

overall chip:

P = f*CL*(VDD-VSS)2 = f*CL*VDD2
74

Reducing
If

P V

P' V '
2

DD

DD

P
5V

2.29
P' 3.3V
2

## EXAMPLE : if V 5V, V ' 3.3V

DD

DD

P
5V
EXAMPLE : if V 5V, V ' 1.8V
7.72
P' 1.8V
2

DD

DD

75

## reducing VDD increases delay

If we reduce VDD to VDD,
t'r
VDD

so

'
'
'
t
R p VDD
VDD
r
Rp

VDD

t'r
5V
EXAMPLE : if VDD 5V,VDD' 3.3V
1.52
t r 3.3V
t'r
5V
EXAMPLE : if VDD 5V,VDD ' 1.8V
2.77
t r 1.8V

## reducing VDD decreases noise immunity

(more careful design necessary!)
76

Reduction

## Use lower VDD to reduce power

Compensate for higher delays by
Using newer, smaller, faster IC technology
Trading off more slower logic for less faster logic this is called voltage scaling
Examples (from Tom Burds General Processor Information)
Intel P5 Pentium: VDD=5.0V / fclk=66MHz / P=16W

## Compaq Alpha 21264: VDD=2.0V / fclk=667MHz / P=72W

77

Speed-Power Product
A

## way of characterizing the quality of a logic

family
For static complementary CMOS
1
SP P CV
f

DD

Bottom

to reduce VDD

78