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Total Power Minimization in Glitch-Free

CMOS Circuits Considering Process


Variation
Yuanlin Lu
Intel Corporation, Folsom, CA 95630
Vishwani D. Agrawal
Department of ECE, Auburn University, Auburn, AL 36849

Jan 4-8, 2008

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Outline
Motivation
Problem Statement
Background
Proposed Technique

Statistical reduction of leakage and glitch


power under process variation

Results
Conclusion
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Motivation
Leakage power has become a dominant contributor to
the total power consumption

65nm, leakage is ~ 50% of total power consumption

Glitches consume 20%-70% of dynamic power


Variation of process parameters increases with
technology scaling

both average and standard deviation of leakage power increase


Glitch elimination technique of path balancing becomes
ineffective
Power yield and timing yield are degraded

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One Example: Process Variation


Effect on Leakage and Performance

0.18um CMOS process


20X leakage variation
30% frequency
variation
high frequency but too
leaky chips must be
discarded
low leakage chips with
too low frequency must
also be discarded

too leaky
too slow

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[Ref] S. Borkar, et. al.,


DAC 2003.

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Comparison of Dynamic and Leakage Power


Variation of Un-Optimized C432 (1,000 Samples)
0.50
10% delay variation
20% delay variation
30% delay variation

0.45

P ro b a b ility

0.40
0.35
0.30

Delay
variation

(meannominal)/
nominal

STD /
mean

10%

-0.05%

0.65%

20%

-0.07%

1.12%

30%

-0.16%

1.50%

Leff
variation

(meannominal)/
nominal

STD /
mean

10%

3.10%

6.1%

20%

8.75%

30.7%

30%

25.17%

112.9%

0.25
0.20
0.15
0.10
0.05
0.00

Probability

Normalized Dynamic Power


0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00

10% Leff variation


20% Leff variation
30% Leff variation

Normalized Leakage Power

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Nominal

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Process Variation and Dynamic Power


0.50
10% delay variation
20% delay variation
30% delay variation

0.40

Probability

Dynamic power is normally much


less sensitive to the process
variation due to its approximately
linear relation to process
parameters.

0.30
0.20
0.10

Nominal

0.00

Normalized Dynamic Power

Deterministic path balancing


becomes ineffective under
process variation because the
perfect hazard filtering conditions
can easily be corrupted with a
very slight variation in process
parameters.

Probability

C432 unoptimized for glitches


0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00

10% delay variation


20% delay variation
30% delay variation

Normalized Dyanmic Power

C432 optimized by path balancing


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Previous Work and Problem Statement


Previous Work: Mixed integer linear program
(MILP) for optimum Dual-Vth and delay buffer
assignment for

Minimum leakage
Glitch elimination
Overall delay specification
Lu and Agrawal, CMOS Leakage and Glitch Minimization
for Power-Performance Tradeoff, JOLPE, vol. 2, no. 3,
pp. 1-10, December 2006.
Lu and Agrawal, Statistical Leakage and Timing
Optimization for Submicron Process Variation, Proc. 20th
Int. Conf. VLSI Design, Jan. 2007, pp. 439-444.

Problem Statement: Minimize leakage and glitch


power considering process variation.
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Techniques to Eliminate Glitches


?
path delay difference < gate inertial delay [1]

Hazard Filtering
(Gate/Transistor Sizing)

Increase gate inertial delay


Sizing gate to change gate delay

Path Balancing

1 3

1.5

Decrease path delay difference


Insert delay elements on the
shorter delay signal path

2 0.5

[1] V. D. Agrawal, International Conference on VLSI Design, 1997


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Glitch Elimination
For every gate i:
Without process variation: | Ti ti | Di
With process variation: Prob{ | Ti ti | Di }

Inertial delay
Di

Signal arrival time window


[ ti, Ti]

Di = Xi Di(low Vth) + (1 Xi) Di(high Vth), Xi = [0,1]


Leakage(i) = Xi Leajage(low Vth) + (1 Xi) Leakage (high Vth)

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A Mixed Integer Linear Program


for Leakage and Glitch Power Reduction
Objective function (linear approximation):
Minimize {C1Total leakage + C2Total glitch
suppressing delays}

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MILP Formulation
(Deterministic vs. Statistical)
Deterministic Approach

Statistical Approach

The delay and subthreshold current of


every gate are assumed to be fixed and
without any effect of the process
variation.

Treat delay and timing intervals as random


variables with normal distributions;
leakage as random variable with lognormal
distribution

Basic MILP

Basic MILP

Minimize total leakage while keeping


the circuit performance unchanged.
Minimize

subnom ,i

i gate number

Minimize

subnom ,i

i gate number

Subject to TPOk Tmax k PO

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Minimize total nominal leakage while


keeping a certain timing yield ( ).

Subject to P TPOk Tmax

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k PO

Delay Distribution without Considering


Process Variation
di = Ti-ti

Timing
window
Ti - ti

di <= Ti-ti
with glitch

di = Ti-ti
di <= Ti-ti
with glitch

Timing
window
Ti - ti

di >= Ti-ti
glitch free

di >= Ti-ti
glitch free

Gate delay di

Circuits unoptimized for glitch

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Gate delay di

Circuits optimized for glitch


by path balancing

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Delay Distribution under Process Variation


di = Ti-ti

Timing
window
Ti - ti

di <= Ti-ti
with glitch

di = Ti-ti
di <= Ti-ti
with glitch

Timing
window
Ti - ti

di >= Ti-ti
glitch free

di >= Ti-ti
glitch free

Gate delay di

Circuits unoptimized for glitch

Gate delay di

Circuits optimized for glitch


by path balancing

Glitch power of unoptimized circuits is not sensitive to process variation;


Glitch power of circuits optimized by path balancing is sensitive to process variation.
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Technique of Enhancing the Resistance


of Glitch Power to Process Variations
di =Ti-ti
di <= Ti-ti
with glitch
Timing
window
Ti - ti
di >= Ti-ti
glitch free

Gate delay di

Leave a relaxed margin for process variation resistance in advance


Di Ti t i

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Di 3 Di ( Ti 3 Ti ) ( ti 3 ti )

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Results for C432


Monte Carlo Simulation (15% local
process variation)

statistical =1.04 3/=2.82% (-N)/N=3.63%


determistic =1.14 3/=5.13% (-N)/N=13.53%
0.50

C432 optimized by the


statistical MILP with greater
emphasis on glitch power to
process variation (blue)
C432 optimized by the
deterministic MILP (Purple)

0.30
0.20
0.10
0.00

Normalized Dynamic Power

statistical

N2=1.94 =2.25 /=10.24% (-N1)/N1=16.97%

deterministic N1=1.00 =1.17 /=6.64%

Dynamic Power
(logic simulation)
Subthreshold Leakage
(Spice simulation)

0.20
Probability

Probability

0.40

0.15
0.10
0.05
0.00

Normalized Leakage

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(-N2)/N2=15.22%

Results of MILP: Leakage Power Distribution


of Optimized Dual-Vth C7552

Mean and Standard Deviation of leakage power are reduced by the


statistical method.
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Conclusion
Circuits optimized of glitch suppression can
be seriously degraded by process variation.
Overdesign (3 variation) may reduce
sensitivity to process variation.
Statistical design (specified yields) can give
improved tradeoffs between leakage power,
glitch power and timing.

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Future Work
Iterative MILP
for dual-Vth design

The interdependency of delays of


gates was neglected for simplicity in
our MILP formulation.

gate delay

= 2

8.2ns = 2

3.2

7ns

FF

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8ns

Timing violations were found

LVT design
dual-Vthdesign

3
FF

If any timing violation is found, the


new delays for all LVT cells are
extracted from the current dual-Vth
design and the MILP formulation is
updated correspondingly. A different
optimal solution is then given by the
CPLEX solver with fewer timing
violations. We continue iterations until
all timing violations are eliminated.

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Thank You All !


Questions?
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