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Design of Sequential adder by using

multi bit flip-flop for Power Reduction



The consumption of power has become an important issue in modern VLSI

design. power consumption can be reduced by replacing some flip-flops
with fewer multi-bit flip-flops.

Multi-bit flip-flop is one of the methods for clock power consumption

reduction. This project focuses on reduction of power using multi-bit
flipflops by clock synchronization.

Merging single bit flip-flops into one multi-bit flip-flop avoids duplicate
inverters, lowers the total clock power consumption and reduces the total


A combination table which can store the flip-flops that can be merged to
obtain a multi-bit flip-flop.

Ripple carry adder is used as an application for multibit flip-flop. Highest

1 bit finding algorithm is used to find the highest 1 bit from the output of
Ripple carry adder. This algorithm checks the output of ripple carry adder
in each cycle.

This proposed algorithm is designed and realized using Xilinx Spartan 3E

FPGA and Xilinx ISE software for hardware implementation and analysis
the clock power consumption of single,two,four and eight bit flipflop


To implement the sequential 8 bit ripple carry adder by using multi bit flipflop based highest 1s bit algorithm and to reduced the Flip-flop clock
power, delay and area.



[1]. In-Placement Clock-Tree

Aware Multi-Bit Flip-Flop

This paper introduces a novel This paper minimize the Flipplacement flow with clock-tree
Flop power and Clock
aware flip-flop merging and
when applying
MBFF generation, and
Multi-Flip-Flop only during
proposes the corresponding
algorithms to simultaneously
minimize flip-flop power and
clock latency when applying
MBFFs during placement.

Power This paper introduces an
Optimization based on RTL approach for reducing
Clock Gating
clock power based on clock
The power savings achieved ,
when the size of the circuits is
significant, savings on the power
consumption of the clock tree
are up to 75% larger than those
achieved by applying traditional
clock gating at the clock inputs
of the RTL modules of the


This paper reduce clock power

based on clock gating technique.
But they are designed by using
single bit flipflop. So area
consumption is high.




[3]. A Noble Research on to The multi bit flip-flop technique This paper designed the single
Reduce Clock Power by Using is one of the techniques used to
bit flip-flop to multi bit flipMulti Bit Flip Flops
reduce the clock power. The
flop transformation .but they
power reduction is
are not implemented any
achieved through the merging of
Logic circuits for analysis
flip-flops based on certain timing
[4]. A Reduced Clock-Swing This paper introduces an
Flip-Flop (RCSFF) for 63% RCSFF can reduce the clock
Power Reduction
system power of a VLSI down
to one-third compared to the
conventional flip-flop and it can
reduced area, delay and power

This paper reduce clock power,

area and delay based on RCSFF.
But further more reduced the
clock power, area and delay by
using multi bit flip-flop.but they
are not used multi bit flip-flop.




[5]. Half VDD Clock-Swing

Flip-Flop with Reduced
Contention for up to 60% Power
Saving in Clock

This paper introduces a new This paper reduce the area,clock

low clock swing flip-flop (F/F)
power and delay. But they
are also only used single bit
area,clock ,power and delay.
flipflop. But they are not
used the multi bit flipflop .
But if it is used means futher
reduced the area,power and


In existing system, they are only designed the Multibit Flipflop to reduced
the duplicate inverter compared from single bit flip-flop.

To Analysis and compared the single bit and multi bit flip-flop power

Disadvantage of Existing system

In existing system, only designed the transformation of single bit and

multi bit flip-flop design and combination table and not implemented any
digital logic circuits.

This multi bit flipflop is not implemented / tested in FPGA .

Proposed System

In the proposed work used D-FF this makes low power when compared to other FF
and the output will be easy to processed. After finding that number the particular
bits of FF storage is getting enabled and remaining will be in sleep mode. It reduces
the power consumption and wire length for the MBFF.

Depends upon the FF storage enabled. The combination table is selected for FF
selection. [below Fig shows the single bit flipflop to multi bit flipflop

To analysis the clock power and area consumption of single, two, four and eight
bit flipflop based adder design.

Block Diagram

Addition Waveform

Power consumption in Singlebit FlipFlop

Power consumption in Twobit FlipFlop

Power consumption in Four bit FlipFlop

Power consumption in Eight bit FlipFlop

Switch Interface with FPGA

The above diagram shows interfacing switch with FPGA board

Here one end of the switch is connected with supply and
another end connected with ground as well as FPGA board
If we push the switch to high 1 will be display on the LCD
module and if we push switch to low means 0 will be display
This eight switches are used to give the input for the addition

LED Interface with FPGA

The above figure shows the FPGA interfacing with LEDs and these LEDs
are used to find the added output
One end of the LED connected with FPGA and another end connected with
If the high value (1) comes to LED means light will glow otherwise (0)
it will not glow

LCD Interface with FPGA

The above diagram shows the interfacing LCD module with FPGA board

Typically LCD module has three control terminal and eight data terminal

The three control terminals are EN,R/W and RS and these are used to
control the LCD module

This LCD module used to shows the added value as well as find the
selection of flip flop

Working of hardware

In the hardware section we have two eight bit switches, these switches are
used to give the input to the adder

The addition process takes place in FPGA board

Then the added output shows in LCD module and LEDs

The LCD module shows the output according to the highest 1 bit

Working of proposed system

in hardware

Step 1 : Give 8 bit input through the 8 switch connected with FPGA board

Step 2 : Give another 8 bit input through the 8 switch connected with
FPGA board

Step 3 : The addition operation is done by FPGA xc3s100e

Step 4 : The result can view in LCD module and also onboard LED light

Working of proposed system

in hardware (2)

Step 5 : If the MSB of output is binary 1 means the MSB will be stored

single bit FF and other 8 bit result will be stored in 8 bit FF

Step 6 : If the fourth bit of the output is 1 and before the fourth bit all 0
means 4 bit value only stored in 4 bit FF

Strep 7 : Similarly for all case

Advantage of proposed system

In proposed system, The multibit flipflop is implemented with adder logic

circuit with the concept of highest 1s bit algorithm and combination table

The adder logic circuit is implemented in Xilinx FPGA and analysis the
clock power and area consumption of the logic circuit.

Hardware/Software requirement

Power analysis Tool

: Spartan 3E
: XC3S100 E VQG100C
: Xilinx ISE 12.4I
: ISE Simulator
: Xpower analysis

In this paper, we have introduced a new placement flow with clock-tree aware flipflop merging and MBFF generation. We have also proposed the corresponding
algorithms to simultaneously minimize power and clock latency when applying
MBFFs during placement and we also designed multiple bit Flip-Flop up to eight
bit and we are used that Flip-Flop for storing the output of eight bit adder. We have
showed the power comparison for single bit, two bit, four bit and eight bit Flip-Flop
with eight bit adder using Xilinx 12.4i software. Finally we have implemented this
adder in Spartan - 3E FPGA board.


Using multi-bit flip-flop for clock power saving by Design Compiler

Automatic register banking for low power clock trees.

A reduced clock-swing flip-flop

Effective and Efficient Approach for Power Reduction by Using Multi-Bit


Power-driven flip-flop merging and relocation.

Using multibit register inference to save area and power

Thank You