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Digital

Fundamentals
Tenth Edition

Floyd

Chapter 7

Floyd, Digital Fundamentals, 10th ed

2008 Pearson
Education
© 2009 Pearson Education,©Upper
Saddle River,
NJ 07458. All Rights Reserved

Summary
Latches
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs; with NAND gates, it responds to active-LOW
inputs.
R

S

Q

Q

NOR Active-HIGH Latch
Floyd, Digital Fundamentals, 10th ed

S

R

Q

Q

NAND Active-LOW Latch

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (0). To SET the latch
(Q = 1), a momentary HIGH signal
is applied to the S input while the R
remains LOW.
To RESET the latch (Q = 0), a
momentary HIGH signal is
applied to the R input while the S
remains LOW.

0 R

10
0 S
0 R

01

01
0 S

Floyd, Digital Fundamentals, 10th ed

01

Q

Latch
initially
RESET
Q

Q

Latch
initially
SET
Q

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (1). To SET the latch
(Q = 1), a momentary LOW signal
is applied to the S input while the R
remains HIGH.
To RESET the latch a momentary
LOW is applied to the R input
while S is HIGH.
Never apply an active set and
reset at the same time (invalid).
Floyd, Digital Fundamentals, 10th ed

1 S

01

01
1 R
1 S

01

Q

Latch
initially
RESET
Q

Q

Latch
initially
01 SET
1R

Q

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

To SET any of the latches.Summary Latches The active-LOW S-R latch is available as the 74LS279A IC. It features four internal latches with two having two S inputs. S-R latches are frequently used for switch debounce circuits as shown: VCC (2) (3) (1) (6) (5) (11) (12) (10) 2 S S R R 1 Floyd. 10th ed (15) Q (14) Position 1 to 2 Position 2 to 1 1S1 1S2 (4) 1Q (7) 2Q (9) 3Q (13) 4Q 1R 2S 2R 3S1 3S2 3R 4S 4R 74LS279A © 2009 Pearson Education. Digital Fundamentals. NJ 07458. the S line is pulsed low. It is available in several packages. All Rights Reserved . Upper Saddle River.

called enable (EN) that must be HIGH in order for the latch to EN respond to the S and R inputs. 10th ed © 2009 Pearson Education. All Rights Reserved .Summary Latches A gated latch is a variation on the basic latch. S The gated latch has an additional Q input. NJ 07458. R Assume Q starts LOW. Show the Q output with Q relation to the input signals. Keep in mind that S and R are only active when EN is HIGH. S R EN Q Floyd. Digital Fundamentals. Upper Saddle River.

Upper Saddle River. Floyd. All Rights Reserved . 10th ed © 2009 Pearson Education. Digital Fundamentals. NJ 07458.Summary Latches The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D Q EN D Q EN Q Q A simple rule for the D latch is: Q follows D when the Enable is active.

then there is no change in the output and it is latched.Summary Latches The truth table for the D latch summarizes its operation. NJ 07458. 10th ed Outputs D EN Q Q Comments 0 1 X 1 1 0 0 1 Q0 1 0 Q0 RESET SET No change © 2009 Pearson Education. If EN is LOW. All Rights Reserved . Digital Fundamentals. Upper Saddle River. Inputs Floyd.

Floyd.Summary Latches D Q EN Determine the Q output for the D latch. given the inputs shown. Digital Fundamentals. Upper Saddle River. Q D EN Q Notice that the Enable is not active during these times. so the output is latched. All Rights Reserved . 10th ed © 2009 Pearson Education. NJ 07458.

A flip-flop is a clocked device. The active edge can be positive or negative. in which only the clock edge determines when a new bit is entered. 10th ed D Q C Q (a) Positive edge­triggered Q (b) Negative edge­triggered © 2009 Pearson Education. NJ 07458.Summary Flip-flops A flip-flop differs from a latch in the manner it changes states. All Rights Reserved . Digital Fundamentals. D Q C Dynamic input indicator Floyd. Upper Saddle River.

10th ed CLK Outputs Q Q Comments 1 0 0 1 SET RESET (b) Negative-edge triggered © 2009 Pearson Education. NJ 07458. Digital Fundamentals. The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow.Summary Flip-flops The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock. Upper Saddle River. Inputs D 1 0 CLK Outputs Inputs Q Q Comments D 1 0 0 1 SET RESET 1 0 (a) Positive-edge triggered Floyd. otherwise it is latched. All Rights Reserved .

Inputs Floyd. When both J and K = 1. it has two inputs. Upper Saddle River.Summary Flip-flops The J-K flip-flop is more versatile than the D flip flop. All Rights Reserved . Digital Fundamentals. 10th ed J K 0 0 1 1 Outputs CLK Q Q Comments 0 1 0 Q0 0 1 Q0 1 0 1 Q0 Q0 No change RESET SET Toggle © 2009 Pearson Education. NJ 07458. In addition to the clock input. the rising edge). the output changes states (toggles) on the active clock edge (in this case. labeled J and K.

Summary Flip-flops Q J CLK Determine the Q output for the J-K flip-flop. Upper Saddle River. given the inputs shown. K Q Notice that the outputs change on the leading edge of the clock. Digital Fundamentals. Set Toggle Set Latch CLK J K Q Floyd. All Rights Reserved . NJ 07458. 10th ed © 2009 Pearson Education.

the output will only change once for each clock pulse. Q is HIGH and the flip-flop will toggle on the next clock edge. All Rights Reserved . but you can hardwire a toggle mode by connecting Q back to D as shown. Because the flip-flop only changes on the active edge.Summary Flip-flops A D-flip-flop does not have a toggle mode like the J-K flipflop. NJ 07458. Floyd. 10th ed CLK Q CLK Q D flip-flop hardwired for a toggle mode © 2009 Pearson Education. Digital Fundamentals. Upper Saddle River. This is useful in some counters as you will see in Chapter 8. D For example. if Q is LOW.

A J-K flip flop with active LOW preset and CLR is shown. Digital Fundamentals. These inputs are usually active LOW. 10th ed © 2009 Pearson Education. Q J CLK Q K CLR Floyd. Most flipflops have other inputs that are asynchronous. Upper Saddle River. NJ 07458. All Rights Reserved . PRE Two such inputs are normally labeled preset (PRE) and clear (CLR).Summary Flip-flops Synchronous inputs are transferred in the triggering edge of the clock (for example the D or J-K inputs). meaning they affect the output independent of the clock.

10th ed © 2009 Pearson Education. NJ 07458. Upper Saddle River. given the inputs shown.Summary PRE Flip-flops Q J CLK Determine the Q output for the J-K flip-flop. Q K CLR Set Toggle Set Reset Toggle Latch CLK J K PRE Set Reset CLR Q Floyd. All Rights Reserved . Digital Fundamentals.

It is measured between the 50% level of the clock to the 50% level of the output transition.Summary Flip-flop Characteristics Propagation delay time is specified for the rising and falling outputs. Upper Saddle River. Even faster logic is available for specialized applications. NJ 07458. 10th ed © 2009 Pearson Education. All Rights Reserved . Floyd. Digital Fundamentals. 50% point on triggering edge CLK CLK Q 50% point on LOW-toHIGH transition of Q tPLH 50% point 50% point on HIGH-toLOW transition of Q Q tPHL The typical propagation delay time for the 74AHC family (CMOS) is 4 ns.

Summary Flip-flop Characteristics Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Upper Saddle River. All Rights Reserved . The 74AHC family has specified delay times under 5 ns. Again it is measured from the 50% levels. Digital Fundamentals. NJ 07458. PRE 50% point 50% point Q tPHL Floyd. 10th ed CLR 50% point 50% point Q tPLH © 2009 Pearson Education.

NJ 07458. D CLK Hold time. D CLK Set-up time. Setup time is the minimum time for the data to be present before the clock. tH Floyd. 10th ed © 2009 Pearson Education.Summary Flip-flop Characteristics Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop. Upper Saddle River. Digital Fundamentals. All Rights Reserved . ts Hold time is the minimum time for the data to remain after the clock.

minimum pulse widths for various inputs. The quiescent power dissipated is 1. and power dissipation.1 mW. Therefore. the speed-power product is 5 pJ Floyd. the average propagation delay is 4. All Rights Reserved . What is the speed-power product for 74AHC74A? Use the data from Table 7-5 to determine the answer.Summary Flip-flop Characteristics Other specifications include maximum clock frequency. From Table 7-5. The power dissipation is the product of the supply voltage and the average current required. 10th ed © 2009 Pearson Education. Upper Saddle River. The unit is energy. NJ 07458. A useful comparison between logic families is the speed-power product which uses two of the specifications discussed: the average propagation delay and the average power dissipation. Digital Fundamentals.6 ns.

Upper Saddle River. Digital Fundamentals. as frequency dividers. a group of flip-flops are connected to parallel data lines and clocked together. for data storage applications. and in counters (which are covered in detail in Chapter 8). All Rights Reserved . C Parallel data input lines R Q3 D Clock Clear Floyd. 10th ed Q2 D C R © 2009 Pearson Education. Data is stored until the next clock pulse.Summary Output lines Q0 Flip-flop Applications Principal flip-flop applications are for temporary data storage. D C R Q1 D C R Typically. NJ 07458.

it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to HIGH HIGH continue to divide by two. A side benefit of frequency division is that the output has an exact 50% duty cycle. two flip-flops will divide fin by 4 (and so on). Digital Fundamentals. All Rights Reserved . Waveforms: QA J fin CLK K QB J fout CLK K fin fout Floyd. Upper Saddle River. NJ 07458. One flip-flop will divide fin by 2. 10th ed © 2009 Pearson Education.Summary Flip-flop Applications For frequency division.

the length of time in the unstable state (tW) is determined by an external RC circuit. NJ 07458.Summary One-Shots The one-shot or monostable multivibrator is a device with only one stable state. REXT CEXT CX Trigger Q RX/CX Q Trigger Q tW Floyd. Digital Fundamentals. Upper Saddle River. +V then returns to its stable state. When triggered. All Rights Reserved . 10th ed © 2009 Pearson Education. it goes to its unstable state for a predetermined length of time. For most one-shots.

Upper Saddle River. 10th ed © 2009 Pearson Education. Digital Fundamentals. even if it occurs in the unstable state. Retriggerable one-shots respond to any trigger. Retriggerable one-shot: Trigger Retriggers Q tW Floyd.Summary One-Shots Nonretriggerable one-shots do not respond to any triggers that occur during the unstable state. If it occurs during the unstable state. All Rights Reserved . the state is extended by an amount equal to the pulse width. NJ 07458.

Digital Fundamentals. Upper Saddle River. Missing trigger due to power failure Triggers derived from ac Retriggers Q Retriggers Power failure indication tW tW tW Floyd. In the event of a power failure.Summary One-Shots An application for a retriggerable one-shot is a power failure detection circuit. NJ 07458. All Rights Reserved . the one-shot is not triggered and an alarm can be initiated. and continue to retrigger the one shot. 10th ed © 2009 Pearson Education. Triggers are derived from the ac power source.

CC R1 (4) (7) RESET (8) VCC DISCH The trigger is a negative-going pulse. (6) (2) C1 Floyd. Digital Fundamentals.1R1C1 (1) © 2009 Pearson Education. Upper Saddle River. NJ 07458. All Rights Reserved .1R1C1. including as a one-shot.Summary The 555 timer The 555 timer can be configured in various ways. 10th ed THRES OUT TRIG CONT GND (3) (5) tW = 1. The pulse width is determined by R1C1 and is approximately tW +V = 1. A basic one shot is shown.

Digital Fundamentals.1R1C1 = 1. 10th ed THRES OUT TRIG CONT GND (3) (5) tW = 1. Upper Saddle River.2 F) = 24.Summary The 555 timer Determine the pulse width for the circuit shown. NJ 07458.2 ms +VCC +15 V (4) R1 10 k (7) RESET (8) VCC DISCH (6) (2) C1 2.2 F Floyd.1R1C1 (1) © 2009 Pearson Education. tW = 1.1(10 k)(2. All Rights Reserved .

44  R1  2 R2  C1 (4) R1 (7) The frequency and duty cycle are set by these components. Digital Fundamentals. Upper Saddle River.Summary The 555 timer The 555 can be configured as a basic astable multivibrator with the circuit shown. NJ 07458. The output +V frequency is given by: CC f  1. 10th ed © 2009 Pearson Education. R2 (6) (2) C1 (8) RESET DISCH VCC THRES OUT TRIG CONT GND (3) (5) (1) Floyd. In this circuit C1 charges through R1 and R2 and discharges through only R2. All Rights Reserved .

001 0.Summary The 555 timer Given the components. Digital Fundamentals.0 C1 (F) (4) R1 R2 0. you can read the frequency from the chart.01 0.1 (6) (2) 0. Alternatively. Upper Saddle River. 10th ed © 2009 Pearson Education.0k 10k 100k f (Hz) Floyd. you can use the chart to pick components for a desired frequency. +VCC 100 10 (7) 1.0 10 100 1. NJ 07458.1 C1 (8) RESET DISCH VCC THRES OUT TRIG CONT GND (3) (5) (1) 1. All Rights Reserved .

J­K flip­flop A type of flip­flop that can operate in the SET. Floyd. Latches and flip­flops are  bistable multivibrators. All Rights Reserved . Bistable Having two stable states.Selected Key Terms Latch   A bistable digital circuit used for storing a bit. no­change. NJ 07458.  RESET. 10th ed © 2009 Pearson Education. Clock A triggering input of a flip­flop. and toggle modes. Upper Saddle River. Digital Fundamentals.  D flip­flop A type of bistable multivibrator in which the  output assumes the state of the D input on the  triggering edge of a clock pulse.

Floyd. NJ 07458. Set­up time The time interval required for the input levels to be  on a digital circuit. Upper Saddle River. 10th ed © 2009 Pearson Education. Digital Fundamentals. Hold time The time interval required for the input levels to remain steady to a flip­flop after the triggering  edge in order to reliably activate the device. Timer A circuit that can be used as a one-shot or as an oscillator. All Rights Reserved .Selected Key Terms Propagation  The interval of time required after an input signal  delay time   has been applied for the resulting output signal to  change.

D is LOW d. Enable is not active c. Upper Saddle River. The output of a D latch will not change if a.1. 10th ed © 2009 Pearson Education. All Rights Reserved © 2008 Pearson Education . NJ 07458. Digital Fundamentals. all of the above Floyd. the output is LOW b.

Upper Saddle River.2. The D flip-flop shown will D a. toggle on the next clock pulse Floyd. 10th ed © 2009 Pearson Education. set on the next clock pulse b. Digital Fundamentals. latch on the next clock pulse CLK Q CLK Q d. NJ 07458. All Rights Reserved © 2008 Pearson Education . reset on the next clock pulse c.

All Rights Reserved © 2008 Pearson Education .3. the number of inputs that are asynchronous is PRE a. 1 b. For the J-K flip-flop shown. 2 c. NJ 07458. 4 Q J CLK Q K CLR Floyd. Digital Fundamentals. 10th ed © 2009 Pearson Education. 3 d. Upper Saddle River.

Digital Fundamentals. For the inputs shown. Upper Saddle River. 3 d. 2 c. 4 Floyd.4. 1 b. 10th ed CLK J K 1 2 3 4 © 2009 Pearson Education. Assume the output is initially HIGH on a leading edge triggered J-K flip flop. NJ 07458. the output will go from HIGH to LOW on which clock pulse? a. All Rights Reserved © 2008 Pearson Education .

5. tPHL b. Upper Saddle River. 10th ed Q 50% point on LOW-toHIGH transition of Q ? © 2009 Pearson Education. tPLH 50% point on triggering edge CLK c. NJ 07458. Digital Fundamentals. set-up time d. The time interval illustrated is called a. All Rights Reserved © 2008 Pearson Education . hold time Floyd.

Digital Fundamentals. tPHL b.6. All Rights Reserved © 2008 Pearson Education . hold time Floyd. NJ 07458. Upper Saddle River. 10th ed D CLK ? © 2009 Pearson Education. tPLH c. set-up time d. The time interval illustrated is called a.

7. 10th ed fin CLK K QB J fout CLK K © 2009 Pearson Education. Digital Fundamentals. frequency divider Floyd. frequency multiplier d. The application illustrated is a a. astable multivibrator HIGH HIGH b. data storage device QA J c. All Rights Reserved © 2008 Pearson Education . Upper Saddle River. NJ 07458.

Digital Fundamentals. frequency multiplier d. NJ 07458. data storage device C R c. All Rights Reserved © 2008 Pearson Education . 10th ed C R © 2009 Pearson Education.8. Upper Saddle River. The application illustrated is a Output lines Q0 D C a. frequency divider Q2 D C Parallel data input lines R Q3 D Clock Clear Floyd. astable multivibrator R Q1 D b.

The output will be a a. series of 16. constant HIGH Floyd.9. A retriggerable one-shot with an active HIGH output has a pulse width of 20 ms and is triggered from a 60 Hz line. NJ 07458. series of 20 ms pulses c. 10th ed © 2009 Pearson Education. All Rights Reserved © 2008 Pearson Education . Digital Fundamentals. constant LOW d.7 ms pulses b. Upper Saddle River.

Digital Fundamentals. 10th ed © 2009 Pearson Education. astable multivibrator b. frequency divider (4) R1 (7) R2 (6) (2) C1 (8) RESET DISCH VCC THRES OUT TRIG CONT GND (3) (5) (1) Floyd. monostable multivibrator c.10. frequency multiplier d. The circuit illustrated is a +VCC a. Upper Saddle River. All Rights Reserved © 2008 Pearson Education . NJ 07458.

d 5. NJ 07458. Upper Saddle River. 10th ed 1. c 9. b 6. b 4. All Rights Reserved . a © 2009 Pearson Education. d 2. b 10. Digital Fundamentals. b 8. d 7.Answers: Floyd. d 3.