Digital Logic Design

MELJUN CORTES,BSCS,ACS Department of ICT Faculty of Information Technology

MELJUN

About
 Author: MELJUN CORTES,BSCS,ACS  Office:
Department of Computer Science Faculty of Information Technology SAINT COLUMBAN COLLEGE

 Mobile: 09295141799  Email: j_cortes2005@yahoo.com *** WEBSITE: http://meljuncortes.blogspot.com http://meljun.ning.com http://www.meljun2010.multiply.com
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MELJUN

Content
1. Introduction 2. Function Minimization Methods 3. Larger Combinational Systems 4. Sequential Systems 5. Hardware Design Languages

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MELJUN

1. Introduction
1.1. Review of Number Systems 1.2. Switching Algebra and Logic Circuits

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MELJUN

Chapter 1. Introduction

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MELJUN

1.1. Review of Number Systems
1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other Codes

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MELJUN

1.1. Review of Number Systems
 1.1.1 Number Representation  1.1.2 Binary Addition  1.1.3 Signed Numbers  1.1.4 Binary Subtraction  1.1.5 Binary Coded Decimal (BCD)  1.1.6 Other Codes

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MELJUN

1.1.1. Number Representation

 Numbers are normally written using a positional number system:

N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m
– Base/radix: b (the number of digits) – Digits: 0..(b-1) • 0 ≤ ai ≤ (b-1) – Binary: b=2, digits:0,1 – Decimal: b=10, digits: 0,1,2,3,4,5,6,7,8,9 – Octal: b=8, digits: 0,1,2,3,4,5,6,7 – Hexadecimal: b=16, digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
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MELJUN

1.1.1. Number Representation

N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m
N (10) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m

N (10) =

i =− m

∑ a .b
i

n

i

11101.11(2) = 1x24+1x23+1x22+0x21+1x20+1x2-1 +1x2-2 = 29.75(10)
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MELJUN

1.1.1. Number Representation

 Decimal:
– b=10 – Digits: 0,1,2,3,4,5,6,7,8,9

N (10 ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a−m
– Eg:

ai = 0..9

539.45(10) = 5x102+3x101+9x100+4x10-1+5x10-2

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MELJUN

1.1.1. Number Representation
 Binary:
– b=2 – Digits: 0,1

bit – binary digit

N ( 2 ) = an an −1an −2 ...a1a0 .a−1a− 2 ...a−m
– Eg:
= 11.375(10)
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ai = 0,1

N (10) =
-1 -2

1011.011(2) = 11 + 0*2 + 1*2 +1*2-3 =11 + 0 + 0.25 + 0.125

i =− m

∑ a .2
i

n

i

1.1.1. Number Representation
 Binary (cnt’)
– n-bit binary number can represent which range?
• an-1 ...a1a0 from 0 to 2n-1

– MSB – Most Significant Bit – LSB – Least Significant Bit

0001 = 1 0010 = 2 0011 = 3 0100 = 4 0101 = 5 0110 = 6 0111 = 7 1000 = 8
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1001 = 9 1010 = 10 1011 = 11 1100 = 12 1101 = 13 1110 = 14 1111 = 15

MELJUN

1.1.1. Number Representation
 Octal:
– b=8 – Digits: 0,1,2,3,4,5,6,7 – Eg:
503.071(8) = 5x82 + 0x81 + 3x80 + 0x8-1 + 7x8-2 + 1x8-3 ai = 0..7

N (8) = an an −1...a1a0 .a−1a− 2 ...a− m

 Hexadecimal:
– b=16 – Eg:

N (16 ) = an an −1...a1a0 .a−1a− 2 ...a− m
ai = 0..F

– Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F 1010 0011(2)= A3(16)
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503.071(16) = 5x162 + 0x161 + 3x160 + 0x16-1 + 7x16-2 + 1x16-3

Convert from base b to base 10

Base b to base 10 conversion
N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m

Eg:0

N (10 ) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m

– 1010.11(2) = 10.75 – 1010.11(8) = 0*80+1*81+0*82+1*83 + 1*81 +1*8-2 = 0+8+0+512+0.125+0.015625
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– A12(16) = 10572 = 2*160 + 1*161 + 10*162 =

110.011(2)=?(10) 110.011(8)=?(10) 110.011(16)=?(10)

6.375 72.0175 272.039...

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Convert from base 10 to base b

 Base 10 to base b conversion
– For integer part: • Divide integer part by b until the result is 0
• Write remainders in reverse order to get the converted result.

– For the odd part after “.”
• Multiply by b until the result is 0

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Convert from base 10 to base 2

 Eg1: 6.625(10) = ?(2)
– The integer part 6 0 2 3 1 2 1 1 2 0 – The odd part after “.” • 0.625 x 2 = 1.25 • 0.25 x 2 = 0.5 • 0.5 x 2 = 1.0

6.625(10) = 110.101(2)

 Eg2: 20.75(10) = ?(2)
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MELJUN CORTES
 20.75(10) = ?(2) 10100.11(2)  20 2  0 10     0 2 5 2 0 1 1 2 0 1 2 2 0.75 * 2 = 1.5 0.5 * 2 = 1.0

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MELJUN CORTES
 20.75(10)=?(8) =10100.11(2) = 24.6(8)  20 8 4  2 2 8 0 0.75 * 8 = 6.0

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Convert from base 2 to base 2n
 Group from right to left n-bit groups and replace the equivalent values in base 2n  Eg:

 101011(2) = ?(8) 1010.110(2) =12.6(8)  101011(2) = ?(16) 1010.110(2) =A.C(16)

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Convert from base 2n to base 2
 Each digit in base 2n is replaced by n bit in base 2.  Eg:

 37A.B(16)=?(2) =

0011 0111 1010 . 1011(2)

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Convert from base i to base j
 If both i and j are powers of 2, use base 2 as an intermediate base:
– Eg: base 8 → base 2 → base 16 – 735.37(8)= 000111011101.01111100(2) = 1DD.7C ?(16)

 Else, use base 10 as an intermediate base:
– Eg: base 5 → base 10 → base 2

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1.1. Review of Number Systems
 1.1.1 Number Representation  1.1.2 Binary Addition  1.1.3 Signed Numbers  1.1.4 Binary Subtraction  1.1.5 Binary Coded Decimal (BCD)  1.1.6 Other Codes

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1.1.2 Binary Addition

Binary long addition similar to decimal long addition.
carry decimal binary 110 11110

A B sum

2565 6754 9319

10110 11011 110001

Eg: 10101(2) + 11011(2) = 110000 ? (2)

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1.1.2 Binary Addition

 Overflow:
– Occur when the result of addition is out of range of representation (the result can not be stored in the predefined number of bits) – In 8-bit computer, the result of addition of two binary numbers 10101010 and 11010011 is 9-bit binary number which can not be stored in 8-bit => overflow

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1.1.2 Binary Addition
 n-bit adder in computer:  A = an-1an-2...a1a0  B = bn-1bn-2...b1b0

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1.1. Review of Number Systems
1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other Codes

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1.1.3 Signed Numbers
 Represent sign and amplitude  Use the most-left-bit to represent sign:
– 0: positive, 1: negative

 Eg: represent signed numbers using 4 bit:
– +5 = 0101, -5 = 1101, -3 = 1011 – Using 3 right bits to represent amplitude, we can represent from -7 to +7. – Drawbacks: • +0 = 0000, -0 = 1000 => complex when calculating

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=> need an other representation

2’s complement representation

 Most left bit is still sign bit  Positive and 0 numbers are expressed in usual binary format.
– The largest number can be represented is 2n-1-1 – n=8 => largest signed number: 28-1-1 = 127

 Negative number a is stored as the binary equivalent of 2n-a in a n-bit system.
– -3 is stored as 28-3=11111101 in a 8-bit system – The most negative number can be stored is -2n-1

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2’s complement representation
 +10 = 0000 1010  - 10 = 28-10 = 1 0000 0000 – 0000 1010 1111 0110 - 10 = 1111 0110  +10 + (-10) = ? 0000 1010  
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1111 0110 1 0000 0000

2’s complement representation

 Procedure to find binary representation of negative number in 2’s complement:
– Find the binary equivalent of the magnitude – Complement each bit (0=>1, 1=>0) – Add 1

 Eg: find representation of -13 in 8-bit signed number system using 2’s complement:
• Magnitude: • Complement: • Add 1: • -13 =
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13 = 0000 1101 1111 0010
+

1 1111 0011

2’s complement representation
 Range of representation:
– Use n bit to represent 2’s complement numbers – Range: -2n-1 => 2n-1-1

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4 bit representation of unsigned and signed (2’s complement)
Binary format 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Unsigned 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signed 0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 -1

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2’s complement representation
 To find the magnitude of a negative number:
– Complement each bit – Add 1

 Eg:   

1001 0110(2) = -106? 0110 1001 + 1 = 106 01101010

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Addition of signed numbers
 The reason that 2’s complement is so popular is the simplicity of addition.  To add any two numbers, no matter what the sign of each is, we just do binary addition on their representation.

-5 1011 +7 0111 +2 0010
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-5

1011

-5 +3 -2

1011 0011 1110

+5 0101 0 0000

Addition of signed numbers
 Overflow
– Occur when? – Add two numbers of the opposite sign? – Add two positive numbers? – Add two negative numbers?
maybe

⇒Overflow occurs when adding two numbers with the same sign and the result is in different sign 0110 0101 = 101 + 0101 0010 = 82 Page  36 1011 0111

1.1. Review of Number Systems
1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other Codes

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1.1.4 Binary Subtraction
 Find the 2’s complement of the second operand, then add.  a – b = a + (-b)  Eg: 7 – 5 = ?
5 0101 1010 + 1 7 -5 2 0111 +1011 0010

-5 1011

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1.1. Review of Number Systems
1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other Codes

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Binary-Coded Decimal - BCD
 BCD:
– Use four bits (a nibble) to represent each of the decimal digits 0 through 9. – Eg: 375 = 0011 0111 0101(BCD)

Decimal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Binary
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

BCD
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101

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1.1. Review of Number Systems
1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other Codes

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ASCII
 American Standard Code for Information Interchange - ASCII  Use seven bits to represent various characters on the standard keyboard as well as a number of control signal

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Problems
1. Convert the following unsigned numbers:
a. b. c. 98.625(10)=?(2) 11011.011(2)=?(10) 6A1.1E(16)=?(8)

2. Represent the following signed numbers: a. -74 in 8-bit signed 2’s complement. b. -74 in 16-bit signed 2’s complement.

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1. Introduction
1.1. Review of Number Systems 1.2. Switching Algebra and Logic Circuits

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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra 1.2.2 Basic Properties of Switching Algebra 1.2.3 Manipulation of Algebraic Functions 1.2.4 Representations of Algebraic Functions 1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra 1.2.2 Basic Properties of Switching Algebra 1.2.3 Manipulation of Algebraic Functions 1.2.3 Representations of Algebraic Functions 1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

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1.2.1 Definition of Switching Algebra
 Switching algebra is binary:
– All variables and constant take on 0 or 1. • Light on/off, switch: up/down, voltage: low/high... – Quantities which are not naturally binary must be coded into binary format. – Three operators: • OR: • AND: • NOT: a+b a.b a’

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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra 1.2.2 Basic Properties of Switching Algebra 1.2.3 Manipulation of Algebraic Functions 1.2.3 Representations of Algebraic Functions 1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

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Basic Properties of Switching Algebra

 P1: Commutative:
• a+b=b+a a.b = b.a

 P2: Associative:
• a + (b + c) = (a + b) + c a.(b.c) = (a.b).c

 P3:
• a+0=a a.1=a

 P4:
• a+1=1 a.0=0

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Basic Properties of Switching Algebra

 P5:
• a + a’ = 1 • a+a=a • n.a=a a . a’ = 0 a.a=a (a)n=a

 P6: no coefficient and no exponent

 P7: complement
• (a’)’ = a

 P8: distributive:
• a.(b+c) = a.b + a.c
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a + b.c = (a+b).(a+c)

Basic Properties of Switching Algebra
Basic Properties of Switching Algebra

 P9: adjacency
• ab + ab’ = a

(a+b)(a+b’)=a

 P10:
• a + a’b = a +b a(a’+b) = ab

 P11: De Morgan
• (a + b)’ = a’b’ (ab)’ = a’ + b’

 P12: absorption
• a + ab = a a(a+b) = a

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Basic Properties of Switching Algebra

 P13: redundant
• ab+b’c+ac = ab+b’c

A

B

C

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Problems
1. Prove the following equalities:

a. xy’+y=x+y b. xy+xz’+yz=xy+x’z c. x’y’z+yz+xz=z d. (x+y)[x’(y’+z’)]’+x’y’+x’z’ = 1 => prove it incorrect

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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra 1.2.2 Basic Properties of Switching Algebra 1.2.3 Manipulation of Algebraic Functions 1.2.4 Representations of Algebraic Functions 1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

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Manipulation of Algebraic Functions

 A literal:
– Is the appearance of a variable or its complement – Eg: x and x’ are two different literals – Expression ab’+bc’d+a’d+e’ has 8 literals

 A product term:
– Is one or more literal connected by AND operators – Expression ab’+bc’d+a’d+e’has 4 product terms – Note: A single literal is also a product term

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Manipulation of Algebraic Functions Manipulation of Algebraic Functions

 A standard product term - minterm:
– Is a product term which includes every variable of the function, either uncomplemented or complemented. – Eg: for a function of four variables a,b,c,d: • the product term a’bc’d is a standard product term • the product term a’bd’ is not

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Manipulation of Algebraic Functions Manipulation of Algebraic Functions  A sum of product - SOP:
– Is one or more product terms connected by OR operators – Eg: ab’c+abc’+a’c+a’ »d

 A canonical sum – sum of standard product term
– Is a sum of products expression where all terms are standard product terms. – Eg: A function of three variables a,b,c: • ab’c + abc’ + abc is a canonical sum • ab’c + abc’ + a is not
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Manipulation of Algebraic Functions Manipulation of Algebraic Functions

 A minimum sum of products:

– Is one of those SOP expression for a function that has the fewest number of product terms. – If there is more than one expression with fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals. – Eg: • F1(x,y,z) = x’yz’+x’yz+ xy’z’+xy’z+xyz • F2(x,y,z) = x’y+xy’+xyz • F3(x,y,z) = x’y+xy’+xz • F4(x,y,z) = x’y+xy’+yz
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F3,F4 are minimum SOP of F1

Manipulation of Algebraic Functions Manipulation of Algebraic Functions

 A sum term:

– Is one or more literals connected by OR operators – Eg: • a + b’ + c’ • b’

 A standard sum term - maxterm:
– Is a sum term that includes each variable of the problem, either uncomplemented or complemented – Eg: For a function of four variables x,y,z,t • x+y+z’+t’ is a maxterm • x+y+t’ is not
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Manipulation of Algebraic Functions Manipulation of Algebraic Functions

 A product of sum – POS:
– Eg:

– Is one or more sum terms connected by AND • (w+x’+y’)(w+y+z’)(w+x+z) •w

 A canonical product – product of standard sum terms:
– Is a product of sum term where all sum terms are standard

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Manipulation of Algebraic Functions Manipulation of Algebraic Functions
– fewest number of terms – the same number of terms => fewest number of literals

 A minimum POS is defined the same way as SOP:

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Canonical forms

 Properties of minterm/Maxterm:
– mimj=0 if i≠j =mi if i=j – Mi+Mj=1 = Mi if i≠j if i=j

– mi=Mi’ and Mi=mi’ for every i

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Canonical forms

 An algebraic expression of a Boolean function can be derived from a given truth table in two ways:
– By summing (ORing) those minterm for which the function takes a value 1. – By multiplying (ANDing) those maxterm for which the function takes a value 0.

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Canonical forms

Decimal x2 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1

x1 0 0 1 1 0 0 1 1

x0 0 1 0 1 0 1 0 1

f 0 1 0 0 1 1 1 1

f(x2,x1,x0)=m1+m4+m5+m6+m7 =Σ(1,4,5,6,7)
Canonical sum-of-products (SOP)

f(x2,x1,x0)=M0M2M3 = Π(0,2,3)
Canonical product-of-sums (POS)

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F(a,b,c)= abc’+a’b’

Decimal 0 1 2 3 4 5 6 7

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

f 1 1 0 0 0 0 1 0

F(a,b,c)=m0+m1+m6
– ∑(0,1,6)

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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra 1.2.2 Basic Properties of Switching Algebra 1.2.3 Manipulation of Algebraic Functions 1.2.4 Representations of Algebraic Functions 1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

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1.2.4 Representations of Algebraic Functions
 Truth table  Venn diagram  Karnaugh map

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Truth table
 List all the possible binary combinations of the independent variables and display the corresponding binary values of dependant variables.

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Truth table
 n independent variables and m dependant functions: 2n rows n+m columns
3 independent variables 2 dependent functions

23 rows

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Venn diagram

 Venn diagram using ‘space’ to present logic  F(A,B)=A.B

A

B

C

F(A,B,C)=C.not(B)
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Venn diagram

A

A

A+B

A.B

A.B
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A+B

Karnaugh map
 A Karnaugh map is a graphical method for representing the true table of a Boolean function.  K-map may be used for any variables number, but often at most six.
C BC A

0

1

00

01

11

10

AB

00 0
0 1 3 2 0 1

01
2 3

1
4 5 7 6

11
6 7

10
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4

5

Karnaugh map (K-map)
 If variables number is n => 2n cells in K-map.  2n cells are arranged in logical pattern for minimization purpose.

BC A

00

01

11

10

0
0 1 3 2

1
4 5 7 6

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Two-variable K-map
 F(A,B)

B A

0
0

1
1

A B

0
0

1
2

0 1

0 1

2

3

1

3

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Two-variable K-map
 F(A,B) = AB

B A

0
0

1
0

0 1

0

1

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Three-variable K-map
 F(A,B,C)

C AB BC A

0

1

00

01

11

10

00
0 1

0
0 1 3 2

01
2 3

1
4 5 7 6

11
6 7

10
4 5

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Three-variable K-map
 F(x,y,z) = xyz + yz’ + x

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

F 0 0 1 0 1 1 1 1
x yz

z

0

1

00
0 1

01
0 1

11
0 1

10
1 1

xy

00 0 1 01 11 10

0 1 1 1

0 0 1 1

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Four-variable K-map

 F(A,B,C,D)
AB

CD

00

01

11

10

00 01 11 10

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Four-variable K-map
 F(A,B,C,D) = AB + CD’ + BCD

CD AB

00
0 0 1 0

01
0 0 1 0

11
0 1 1 0

10
1 1 1 1

00 01 11 10

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Five-variable K-map

E

0

1

CD 00 01 11 10 CD 00 01 11 10 AB AB 00 00 01 01 11 11 10 10 5 variables Karnaugh Map consists of two 4 variables Karnaugh Map connected up/down.

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Six-variable K-map

E

F

0

1 CD 00 01 11 10 AB 00 1 1 01 11 1 1 10 1 1 CD 00 01 11 10 AB 00 1 1 01 11 1 1 10 1 1

CD 00 01 11 10 AB 00 1 1 0 01 1 1 11 1 1 10 CD 00 01 11 10 AB 00 1 1 1 01 1 1 11 1 1 10

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Karnaugh map with don’t care

CD AB 00 01 11 10

00

01

11 1

10 1

1 −

1 − − − − −

don’t care ~ input conditions that not occur

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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra 1.2.2 Basic Properties of Switching Algebra 1.2.3 Manipulation of Algebraic Functions 1.2.4 Representations of Algebraic Functions 1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

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Basic logic gates

AND

OR

NOT

A 0 0 1 1

B 0 1 0 1

out 0 0 0 1

A 0 0 1 1

B 0 1 0 1

out 0 1 1 1

A 0 1

out 1 0

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Basic logic gates
NAND NOR XOR

A 0 0 1 1
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B 0 1 0 1

out 1 1 1 0

A 0 0 1 1

B 0 1 0 1

out 1 0 0 0

A 0 0 1 1

B 0 1 0 1

out 0 1 1 0

Implementation of Functions with AND, OR
 Assume all inputs are available in uncomplemented and complemented

F2 = x’y+xy’+xz
Page  87

F1 = x’yz’+x’yz+xy’z’+xy’z+xyz

Implementation of Functions with AND, OR, NOT
 Complemented inputs can be produced using inverters NOT:

X

Y

F

Z

Page  88

Multilevel circuits
 A circuit is called n-level circuit if the maximum number of gates through which one signal must pass from input to output

two-level circuit
Page  89

three-level circuit

Implementation of Functions with NAND
 Using equivalent change steps, every expression can be represented using only NAND gates.

OR A NOT A A.B B (A’.B’)’ =A+B

B
Page  90

AND

Implementation of Functions with NAND

 Represent the following expression using only NAND:
– F(a,b,c) = ab + bc’ + b’ =

ab + bc + b = ab + bc + b = ab.bc.b

Page  91

Implementation of Functions with NOR
 Using equivalent change steps, every expression can be represented using only NOR gates.
U8A

A' A
7402N U9A

U7A

( A' + ) ' = B B' A.

B

7402N

B'

7402N

A

U3A

A) A' 7402N ( A+ ' =
U10A U11A

Page  92

7402N

7402N

Implementation of Functions with NOR

 Represent the following expression using only NOR:
– F(a,b,c) = ab + bc’ + b’

Page  93

Chapter 2. Logic Function Minimization Methods

Page  94

2. Function Minimization Methods
2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method

Page  95

2. Function Minimization Methods
 What is minimization?
– Number of operands is minimal and number of literal in each operand is minimal

 Why minimization needed?
– Minimize electronic components used to construct the circuit to implement that expression

Page  96

2. Function Minimization Methods
2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method

Page  97

2.1. Algebraic Method
 Use algebraic properties to minimize expressions  Drawback:
– Heuristic, depending on experience – no formal method/procedure – Manually – Not sure whether the last expression is minimal or not

Page  98

2.1. Algebraic Method
 Eg: Minimize these expressions using algebraic method:
– F0(x,y,z)=xyz+x’yz+xy’z+xyz’ – F1(a,b,c,d)=ab+abc+a’cd+a’c’d+a’bcd’ – F2(A,B,C,D)= ( A + BC ) + A.( B + C )( AD + C ) – F3(x,y,z)=(x+y)(x+y+z’)+y’ – F4(a,b,c,d)=(a+b’+c)(a+c’)(a’+b’+c)(a+c+d)

Page  99

2. Function Minimization Methods
2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method

Page  100

2.2 The Karnaugh Map Method
1. Minimum Sum of Product Expressions Using the Karnaugh Map 2. Don’t Cares 3. Product of Sums 4. Minimum Cost Gate Implementation 5. Five- and Six-Variable Maps 6. Multiple Output Problems

Page  101

Implicant, Prime Implicant

 An implicant of a function is a product term that can be used in a SOP

CD AB

00
1

01

11
1 1

10

Implicants of F
Minterm A’B’C’D’ A’B’CD A’BCD ABC’D’ ABCD’ ABC’D ABCD Groups of 2 A’CD BCD ABC’ ABD ABC ABD’ Groups of 4 AB

00 01 11 10
Page  102

1

1

1

1

Implicant, Prime Implicant
 A prime Implicant is an implicant which can not be contained in any other implicants.
CD AB

00
1

01

11 C
1

D BC 10
1

B D

*

00 01

1 1 1 1

1 1 1 1

B D*
11

AD
Page  103

AB

10

Essential Prime Implicant
 Essential PI is a PI which contains at least one minterm which is not contained in other PI.
CD AB

00
1

01

11 C
1

D BC 10
1

B D
minterm 0 is only contained in PI B’D’ minterm 5 is only contained in PI BD => BD & B’D’ are two Essential PI

*

00 01

1 1 1 1

1 1 1 1

B D*
11

AD
Page  104

AB

10

2.2.1 Minimum Sum of Product Expressions
 Rules to minimize using K-map:
– Rule 1: Fill K-map cells with corresponding values – Rule 2: Group adjacent cells whose values are 1. Number of cells is 2n. – Rule 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables.

Page  105

2.2.1 Minimum Sum of Product Expressions
 Step 2: Group adjacent cells whose values are 1. Number of cells is 2n.
CD AB

00

01

11

10

CD AB

00

01

11

10

00 01
1 1 1

00
1 1 1

01 11 10

1

11 10
Page  106

1

1

1

1

1

1

1

2.2.1 Minimum Sum of Product Expressions
 Step 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables.
CD AB

00

01

11

10
21 cells => eliminate 1 variable

00 01 11 10
Page  107

1

1

F(A,B,C,D) = A’BC’ + AC
1 1

22 cells => eliminate 2 variables
1 1

2.2.1 Minimum Sum of Product Expressions
 Example 1: Minimize these functions using K-map:
– a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14) – b. F(A,B,C,D) = R(1,3,5,8,9,13,14,15) – c. F(A,B,C,D) = R(2,4,5,6,7,9,12,13) – d. F(A,B,C,D)= R(1,3,4,5,7,9,13,14,15) – e. F(A,B,C,D)=R(1,3,4,6,9,11,12,14)

Page  108

– a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)

= BC’D + AB’D + BCD’ + A’B’D’
CD AB

00

01

11

10

00
1 1 1 1

01 11 10

1

1

1 1

Page  109

– b. F(A,B,C,D) = R(1,3,4,6,9,11,12,14)

= B’D + BD’
CD AB

00

01
1

11
1

10

00 01 11 10
1

1

1

1

1 1

Page  110

2.2 The Karnaugh Map
1. Minimum Sum of Product Expressions Using the Karnaugh Map 2. Don’t Cares 3. Product of Sums 4. Minimum Cost Gate Implementation 5. Five- and Six-Variable Maps 6. Multiple Output Problems

Page  111

2.2.2 Don’t care
 If the function has don’t care values in cells:
– Cells with don’t care values

can be grouped with ‘1’ cells
– Do not group only don’t

care cells in one group.

CD AB 00 01 11 10

00

01

11 1

10 1

1 −

1 − − − − −

F ( A, B, C , D) = BC + BC
Page  112

Examples:

F(a,b,c,d)=R(1,3,5,7,12,13) don’t care (0,4,10,15)
CD AB

00

01

11

10

00
1 1 1 1

01 11

-

1 1 -

10
Page  113

2. Function Minimization Methods
2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method

Page  114

2.3 Quine-McCluskey Method
1. Quine-McCluskey Method for One Output 2. Iterated Consensus for One Output 3. Prime Implicant Tables for One Output 4. Quine-McCluskey for Multiple Output Problems 5. Iterated Consensus for Multiple Output Problems 6. Prime Implicant Tables for Multiple Output Problems

Page  115

2.3. Quine-Mcluskey method

Karnaugh map cannot handle more than 6 variables. Quine-McCluskey method has no limitation with number of variables, and is suitable for computer algorithm. ABC+ABC+ABC+ABC+ABC AB 00 01 11 10
Page  116

C 0 1 1 1 1 1 1

010 *10

110 11*

111 1*0 1**

100 1*1

101 10*

find a pair of numbers of 1 bit difference

Quine-Mcluskey Procedure
 1: Represent minterms in binary numbers  2: Group each minterm by the number of ‘1’ appearance  3: Make set of 1 bit different numbers between neighboring group
• write the difference within parenthesis • mark * to the number which is not included in a set

 4: Make set of 1 bit different sets with the same number in a parenthesis
• append the difference to parenthesis • mark + to the set which is not included in a set

 5: Iterate these step until all the generated set is marked *  6: Select prime implicants
Page   7:117 Convert to logic variable

S1. Represent minterms in binary numbers

f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF +ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF f(A,B,C,D,E,F)=Σ(0,2,6,7,14,8,41,12,15,10)

f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010
Page  118

S2. Grouping

f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 group each term by the appearance of 1
group 0 group 1 group 2 group 3 group 4

no times 000000

once 000010 001000

twice 000110 001100 001010

three times 000111 001110 101001

four times 001111

Page  119

S3 & S4. Making set (1)

group 0 group 1

000000 000010 001000 000110 001010 001100 000111 001110 101001 001111

0 2 8 6 10 12 7 14 41 15

0,2 (2) 0,8 (8) 2,6(4) 2,10(8) 8,10(2) 8,12(4) 6,7(1) 6,14(8) 10,14(4) 12,14(2) 7,15(8) 14,15(1)

find a pair of 1 bit difference between neighboring group write difference within ( )

group 2

group 3

mark to the number not included in any set

group 4
Page  120

S3 & S4. Making set (2)

0,2 (2) 0,8 (8) 2,6(4) 2,10(8) 8,10(2) 8,12(4) 6,7(1) 6,14(8) 10,14(4) 12,14(2) 7,15(8) Page  121 14,15(1)

0,2,8,10(2,8)

find a pair of 1 bit different sets with the same value in ( ) between neighboring group append difference within ( ) Each pair appears in duplicate

2,6,10,14(4,8) 8,10,12,14(2,4)

mark to the set not involved in the next level set

6,7,14,15(1,8)

when all the set is marked finish

S6. Selecting Prime Implicants (1)

minterms (given at first) Prime implicant (   marked )
Page  122

0 41 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) x

2 x x

6 x x

7

8

x

10 12 14 15 41 x x x x x x x x x x x

write x into the position where minterm is included in the prime implicant

inevitable implicant

If only one x in a column, then the row is inevitable implicant

S6. Selecting Prime Implicants (2)

mini term 0 41 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) x 2 x x 6 x x x 7 8 10 12 14 15 41 x x x x x x x x x x x prime implicants
Page  123

mark minterms involved in the inevitable implicants

inevitable implicants

S7. Conversion to logic variables
41 101001 000000 000010 001000 001010 001000 001010 001100 001110 000110 000111 001110 001111 ABCDEF ABDF F=ABCDEF +ABDF +ABCF +ABDE

0,2,8,10(2,8)

8,10,12,14(2,4)

ABCF

6,7,14,15(1,8)
Page  124

ABDE

Examples:

 Minimize the following functions using QuineMcluskey method:
– a.

F(a, b, c, d, e, f) = ab d ef + abce f + bcd f + ab d e f

– b. F(a,b,c,d,e,f) = ∑(17,21,25,29, 44,45,46,47,49,52,53,54,55,47,61)

Page  125

Quine-Mcluskey method with don’t care
 1: Represent logic function in sum of mini terms ==>A  2: Represent don’t care in sum of mini terms ==>B  3: If there exist duplication in A and B, remove from A  4: Apply Quine-McCluskey method for A and B  5: Be careful not to include B in selecting prime implicants

Page  126

Quine-Mcluskey method with don’t care

f=ABCD+BCD+ACD+ABCD+ABCD don’t care AD mini term decimal ABCD 0 0000 1 0001 2 0010 3 0011 5 0101 7 0111 11 1011 13 1101 15 1111
Page  127

first comparison second comparison 0,1(1) 0,2(2) 0,1,2,3(1,2) 1,3(2) 1,5(4) 2,3(1) 1,3,5,7(2,4) 3,7(4) 3,11(8) 3,7,11,15(4,8) 5,7(2) 5,7,13,15(2,8) 5,13(8) 7,15(8) 11,15(4) 13,15(2)

Quine-Mcluskey method with don’t care

0,1,2,3(1,2) 1,3,5,7(2,4) 3,7,11,15(4,8) 5,7,13,15(2,8)

0 x

2 x

11

13

15

ABCD

x x

x x

00** 0**1 **11 *1*1

f=AB+CD+BD

Page  128

Chapter 3. Larger Combinational Systems

Page  129

Introduction
 Logic circuits are divided into two classes:
– Combinational logic circuits • Output signals only depend on current input signals • Memoryless circuits – Sequential logic circuits • Output signals not only depend on current input signals, but also depend on those input signals in the past • Memory circuits

Page  130

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  131

3.1 Delay in Combinational Logic Circuits
 Delay through logic gates
– When the input to a gate changes, the output of that gate doesn’t change immediately; but there is a small delay Δ. – The output is stable after the longest delay path

A B C X F

Page  132

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  133

Half Adder

a 0
a b HA

b 0 1 0 1

Σ 0 1 1 0

r 0 0 0 1 Σ =a ⊕ b r = ab

Σ (Result) r (Carry-out)

0 1 1

a

=1

Half Adder

Σ

b &

r

Page  134

Addition of two n-bit numbers

r3 A= +B = r4 a3 b3 Σ
3

r2 a2 b2 r3 Σ
2

r1 a1 b1 r2 Σ
1

r0 a0 b0 r1 Σ 0

Summation
Page  135

Σ Σ

4 3

Σ

2

Σ

1

Σ

0

Full Adder
Σ i 01
1

ai ri bi

FA

Σ

i

aibi ri

00

11

10

ri+ 1

0

1

ai 0 0 0 0 1 1 1 1
Page  136

bi 0 0 1 1 0 0 1 1

ri 0 1 0 1 0 1 0 1

Σ 0 1 1 0 1 0 0 1

i

ri+ 1

1

1

1

0 0 0 1 0 1 1 1
1
aibi ri

00

01ri+ 1

11

10

0

1

1

1

1

Σ i = ai ⊕ bi ⊕ ri ri+1 = ai bi + ri (ai ⊕ bi)

Combinational logic circuit design procedure
 Problems: design a combinational logic circuit to do smth.  Design procedure:
– S1: Find inputs, outputs and relations. – S2: Construct truth table – S3: For each output, using K-map to minimize from truth table. – S4: Draw the circuit.

Page  137

Example 1
 Problem: Design a combinational logic circuit to implement this operation: M=N+3, N is 3-bit binary number, the number of bit of M is selected properly.  Solution:
– S1: three inputs: n2n1n0

four outputs: m3m2m1m0

Page  138

Example 1
 S1: three inputs: n2n1n0 four outputs: m3m2m1m0  S2: truth table
n2 n1 n0
m0 1 0 1 0 1 0 1 0 1 0 1 1 1 n2 0 0 0 0 0

m3 m2 m1 m0

n2 0 0 0 0 1 1 1 1

n1 0 0 1 1 0 0 1 1

n0 0 1 0 1 0 1 0 1

m3 0 0 0 0 0 1 1 1

m2 0 1 1 1 1 0 0 0

m1 1 0 0 1 1 0 0 1

 S3:

m3 = n2n0 + n2n1
n1n0 00 01 11 10

Page  139

Example 2
 Problem: design a combinational logic circuit to calculate square of a 2-bit binary number.  Solution:
– Step1: find inputs, outputs • Inputs: a1,a0 • Outputs: b3,b2,b1,b0
Ex2

Page  140

Example 2
– Step 2: truth table
a1 0 0 1 1 a0 0 1 0 1 b3 0 0 0 1 b2 0 0 1 0 b1 0 0 0 0 b0 0 1 0 1

– Step3: using K-map to minimize outputs • b3 = a1.a0 • b2 = a1.a0’ b1 = 0 b0 = a0

Page  141

Example 2
– Step 4: Draw circuit • b3 = a1.a0 • b2 = a1.a0’ b1 = 0 b0 = a0
X1 2.5 V X2 2.5 V X3 2.5 V X4 2.5 V

b3
U1A J1

a1
V1Key = A 5V R1 100Ω

7408N U1B

b2 b1 b0

a0
7408N U2A

J2 V2Key = B 12 V

7404N R2 100Ω

Page  142

Full Adder

ri ai bi & & ≥1 =1 =1 Σ
i

ri+ 1

Page  143

Full Adder

ri ai bi HA & =1 =1 Σ
i

HA & ≥1 ri+ 1

Page  144

n-bit Adder

 Serial n-bit adder A = an-1an-2...a1a0 , B = bn-1bn-2...b1b0
an-1 bn-1

an-2 bn-2 rn-1 rn-2 FA

a1

b1 r1

a0

b0

r 0= 0 FA

FA rn

FA

r2 Σ
n
Page  145

Σ

n1 -

Σ
2

n -

Σ
1

Σ
0

Delay = n x Δ?

n-bit Adder

 Parallel n-bit adder: ri+1 = aibi + ri(ai ⊕ bi) Pi = ai ⊕ bi and Gi = aibi → ri+1 = Gi + ri Pi r1 = G0 + r0P0
G1 ≥ 1 r2 G0 ≥ 1 r1

P0 r0

&

G0 P1

&

τ
1

τ
2

Page  146

P0 r0

& τ

r2 = G1 + G0P1 + r0P0P1

τ

Parallel 4-bit addition
a3 b3 a2 b2 a1 b1 a0 b0 r0

Calculate Pi and Gi P3 G3 P2 G2 P1 G1 P0 G0

Carry calculation r4 r3 a 3 b3 a2 r2 b2 a1 r1 b1 r0 a0 b0

Sum calculation

r4 = Σ
Page  147

4

Σ

3

Σ

2

Σ

1

Σ

0

Subtractor
 To subtract a-b, simply add a to 2’s complement of b.  Second choice:
Half Subtractor => Full Subtractor => n-bit Subtractor

Page  148

Subtractor
 Subtractor by using 2’s complement

B3 A3 A2

B2 A1

B1 A0

B0

A

B

A C

B

A C

B

A C

B

C4

C+

FA
S

C3

C+

FA
S

C2

C+

FA
S

C1

C+

FA
S

C

1

S3
Page  149

S2

S1

S0

Adder and Subtractor

A3

B3

A2 B2

A1 B1

A0

B0

MPX

MPX

MPX

MPX

sel
A B A C B A C B A C B

C4

C+

FA
S

C3

C+

FA
S

C2

C+

FA
S

C1

C+

FA
S

C

S3
Page  150

S2

S1

S0

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  151

Decoder
 An nxm decoder is a combinational circuit that converts binary information from n input lines to m output lines, where m≤2n.
– m = 2n => complete decoder

 Fundamental property: only one output is 1 for any given input combination.

Page  152

Decoder
 Complete decoders: m=2n

x1 x2

D0

xn E

. . .

nxm decoder

. . .

D1

x1 x2 x3

D0 3x8 decoder

. . .

D1 D7

Dm-1

Eg: + 3 bit inputs x1,x2,x3. + 8 bit outputs Y0,Y1…Y7
Page  153

Design 3x8 decoder

x1 x2 x3

D0 3x8 decoder

. . .

D1 D7

En

if (En=0) Disable or D0...D7=0 else if (En=1) Function as a 3x8 decoder

Page  154

BCD-to-decimal decoder

N 0

A 0 0 0 0 0 0 0 0 1 1

B 0 0 0 0 1 1 1 1 0 0

C 0 0 1 1 0 0 1 1 0 0

D 0 1 0 1 0 1 0 1 0 1

Y0 1 0 0 0 0 0 0 0 0 0

Y1 0 1 0 0 0 0 0 0 0 0

A B C D

BCD to decimal Decoder

: :

Y0 Y1 Yi Y9

1 2 3 4 5 6 7 8 9

. . . . . . . . . . . . . . . . . . . . .

Y9 0 0 0 0 0 0 0 0 0 1

Page  155

BCD-to-decimal decoder

Y0 = A B C D
CD AB

Y1 = A B C D
Y2 = BCD

00

01

11

10 1

00 01 11 10

Y3 = BCD Y4 = BC D Y5 = BC D Y6 = BC D Y7 = BCD Y8 = AD Y9 = AD

− −

− −

Page  156

Decoder
 4x16 decoder using two 3x8 decoders

x2 x3 x4

D0 3x8 decoder

. . .

D1 D7

x1 3x8 decoder

D8

. . .

D9 D15

Page  157

Decoder implementation of arbitrary functions

x1 x2 x3 x4 4x16 decoder

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

F1

F1(x1,x2,x3,x4)=Σ(0,1,3,8,12)
Page  158

BCD-to-7segment decoder

a f e d g b c
N 0 1 2 3 4 5 A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 1 1 1 1 b 1 1 1 1 1 0 0 1 1 1 c 1 1 0 1 1 1 1 1 1 1 d 1 0 1 1 0 1 1 0 1 1 e 1 0 1 0 0 0 1 0 1 0 f 1 0 0 0 1 1 1 0 1 1 g 0 0 1 1 1 1 1 0 1 1

Each segment is a Light Emitting Diode (LED)

A

K

6 7 8 9

Page  159

BCD-to-7segment decoder

CD AB

00

01

11

10

00 01 11 10

1 0

0 1

1 1

1 1

B D

&


1


1

− −

− −
A C

&

≥1

a = A + C +BD +B D

Page  160

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  161

Encoder
 An encoder is a circuit that performs the function of a decoder in reverse.  An mxn encoder has m inputs, n outputs where m≤2n. The outputs generate the binary codes corresponding to m inputs.  For example: encoder for PC’s keyboard
Key <=> Character <=> Key code 102 keys, 8 bit ASCII

Page  162

Keyboard encoder

‘1’

P1 P2 Pi 1 2 i Encoder A B C D 9 N=i

P9

 9 keys  4-bit key code.

Page  163

Keyboard encoder

N 1 2 3 4 5 6 7 8 9
Page  164

ABCD 0001 0010 0011 0100 0101 0110 0111 1000 1001

A = 1 if (N=8) or (N=9) B = 1 if (N=4) or (N=5) or (N=6) or (N=7) C = 1 if (N=2) or (N=3) or (N=6) or (N=7) D = 1 if (N=1) or (N=3) or (N=5) or (N=7) or (N=9)

Keyboard encoder

N=1

≥ 1

D

N=2 N=3 N=4 N=5 N=6 N=7 N=8 N=9 ≥ 1

C

≥ 1

B

≥ 1

A

Page  165

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders  3.5 Multiplexors  3.6 Demultiplexors  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  166

Multiplexor
 Multiplexor has one output and more than one input.  Function: select one of input for output MUX 2-1
X0

MUX 4-1
Y
X1 X2 X3 C0 C1 Y

X0 X1 C0

control inputs
C0 0
Page  167

C1 0 0 1 1

C0 0 1 0 1

Y X0 X1 X2 X3

Y X0 X1

1

2-to-1 Multiplexor

MUX 2-1
X0 X1 C0 Y

C0 C0 0 1 Y X0 X1 11 1 1 1 10 0 0 0 0 1 1 1 1

X1 0 0 1 1 0 0 1 1

X0 0 1 0 1 0 1 0 1

Y 0 1 0 1 0 0 1 1

X1X0 C0

00

01 1

0 1

Y = X 0C 0 + X1C 0
Page  168

2-to-1 Multiplexor

Page  169

4-to-1 Multiplexor

Y = s1’s0’I0 + s1’s0I1 +s1s0’I2+ s1s0I3

Page  170

Application of multiplexor
 Select source
Source 1 A = a3 a2 a1 a0 B = b3 b2 b1 b0 Source 2

C0

Receiver Y3 Y2 Y1 Y0
Page  171

Application of multiplexor
 Convert parallel-serial
A
a0 a1 a2 a3 C0
C1

C0 1

Y

0 C1 1 0 Y a0 a1 a2 a3 t t t

Page  172

Application of multiplexor
 Implementation of arbitrary functions:

f(A,B) = A Bf(0,0) + A Bf(0,1 + A Bf(1 + A Bf(1 ) ) ,0) ,1

Y = C1C 0X 0 + C 1C 0X1 + C 1C 0X 2 + C 1C 0X 3
f(0,0) Inputs to select function f(0,1) f(1,0) f(1,1) x2 x3 A
Page  173

x0 x1 Y = f(A,B)

C1

C0

Variables

B

Example

0 Inputs to select function 1 1 0

x0 x1 x2 x3 A Y = f(A,B)

C1

C0

Variables

B

 F(A,B) = A’B + AB’

Page  174

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders and Priority Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  175

Demultiplexor

 Demultiplexor has one input and more than one output  Function: select one of outputs for input
DeMUX 1-2
S0 E

C0

S1

S 0 = C0 E S1 = C0 E

Page  176

Demultiplexor 1-4

S0 E S1 S2 S3 C1 C0

Page  177

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders and Priority Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  178

3.7 Three-State Gates (Tristate)
 Three state gates exhibit three states instead of two states. The three states are:
– High : 1 – Low : 0 – High impedance : z • In this state the output is disconnected which is equal to open circuit. In the other words in that state circuit has no logic significant. We can have AND or NAND three-state gates but the most common is threestate buffer gate

Page  179

3.7 Three-State Gates (Tristate)
 We may use conventional gates such as AND or NAND as three-state gates but the most common is three-state buffer gate.  Note that buffer produces transfer function and can be used for power amplification. Three state buffer has extra input control line entering the bottom of the gate symbol (see next slide)

Page  180

Three-State buffer

Three-state buffer
C A Y ---------------------0 0 z 0 1 z 1 0 0 1 1 1

Page  181

Application of three-state buffer
 Three-state buffers can be used to implement multiplexer

Page  182

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders and Priority Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays - ROMs, PLAs and PALs  3.9 Larger Examples
Page  183

3.8 Gate Arrays - ROM, PLA and PAL

 PLA - Programmable Logic Arrays  PAL - Programmable Array Logic  ROM

Page  184

PLA - Programmable logic arrays
 Pre-fabricated building block of many AND/OR gates
– actually NOR or NAND – "personalized" by making or breaking connections among the gates – programmable array block diagram for sum of products form
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Z1 0 0 1 0 0 1 1 1 Z2 1 0 1 0 1 0 1 0 • • • inputs

m0 m1 m2 m3 m4 m5 m6 m7

AND array

product terms

OR array

outputs • • •

Page  185

Before programming
 All possible connections are available before "programming"
– in reality, all AND and OR gates are NANDs

Page  186

After programming
 Unwanted connections are "blown"
– fuse (normally connected, break unwanted ones) – anti-fuse (normally disconnected, make wanted connections)
A B C

AB B'C AC' B'C' A

Page  187

F0

F1

F2

F3

PLA example
 Multiple functions of A, B, C
– F1 = A B C – F2 = A + B + C – F3 = A' B' C' – F4 = A' + B' + C' – F5 = A xor B xor C – F6 = A xnor B xnor C
A B C F1F2F3F4F5 0000 0 1 1 0 0 0010 1 0 1 1 1 0100 1 0 1 1 1 0110 1 0 1 0 0 1000 1 0 1 1 1 1010 1 0 1 0 0 1100 1 0 1 0 0 1111 1 0 0 1 1
Page  188

full decoder as for memory address A B C bits stored in memory A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

F6

F1 F2 F3 F4 F5 F6

PALs and PLAs
 Programmable logic array (PLA)
– what we've seen so far – unconstrained fully-general AND and OR arrays

 Programmable array logic (PAL)
– constrained topology of the OR array – innovation by Monolithic Memories – faster and smaller OR plane
a given column of the OR array has access to only a subset of the possible product terms

Page  189

ROM – Read Only Memories
 Two dimensional array of 1s and 0s
– entry (row) is called a "word" – width of row = word-size – index is called an "address" – address is input – selected word is output
Example: 10 address x 8 data ROM 210 words x 8 ROM 1024 words x 8 ROM 1k x 8 ROM
internal organization 0 n-1 Address bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) n 2 -1 i decoder j 0 word[i] = 0011 word[j] = 1010 1 1 1 1 word lines (only one is active – decoder is just right for this)

Page  190

ROM – Read Only Memories
 Combinational logic implementation (two-level canonical form) using a ROM
F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 1 0 0 F1 0 1 1 0 0 0 0 1 F2 1 1 0 0 1 0 0 0 F3 0 0 0 1 1 0 1 0 ROM 8 words x 4 bits/word

A B C F0 F1 F2 address outputs block diagram

F3

truth table
Page  191

ROM structure
 Similar to a PLA structure but with a fully decoded AND array
– completely flexible OR array (unlike PAL)
n address lines • • • inputs

decoder

2n word lines

memory array n (2 words by m bits)
outputs • • • m data lines

Page  192

3. Larger Combinational Systems
 3.1 Delay in Combinational Logic Circuits  3.2 Adders and Other Arithmetic Circuits  3.3 Decoders  3.4 Encoders and Priority Encoders  3.5 Multiplexers  3.6 Demultiplexers  3.7 Three-State Gates  3.8 Gate Arrays-ROMs, PLAs and PALs  3.9 Larger Examples
Page  193

3.9 Larger Examples
 1. Seven-segment displays  2. Comparator

Page  194

Comparator

 1-bit full comparator:
Gi Li Ei

ai bi

1bit Full Comparator

ai > bi ai < bi ai = bi

Gi=1 Li=1 Ei=1

Gi = ai .bi Li = ai .bi Ei = ai ⊕ bi

Page  195

Comparator
 N-bit parallel comparator:

Page  196

Midterm examination (90’)
 1. Represent the following function in the canonical form SOP: F(A,B,C)=(A+B’)C  2. Use the Quine-McCluskey method to obtain the minimal sum for the following function: F(A,B,C,D,E)= ∑(1,4,6,7,8,9,10,11,15)  3. Design 4x16 decoder using only 2x4 decoders.  4. Design a combinational logic circuit to calculate the following function: M=N+3 where N is BCD number (Binary-Coded Decimal).

Page  197

Midterm examination 2 (90’)
 1. Represent the following function in the canonical form SOP and POS: F(A,B,C)=C  2. Use the Quine-McCluskey method to obtain the minimal sum for the following function: F(A,B,C,D,E)= ∑(1,4,6,7,8,11,12,13,15)  3. Using 3x8 decoder to implement the following function: F(A,B,C) = AB + B’C  4. Design a combinational logic circuit to calculate the following function: M=N+5 where N is BCD number (Binary-Coded Decimal).

Page  198

Chapter 4. Sequential Systems

Page  199

4. Sequential Systems
 4.1 Definitions  4.2 State Tables and Diagrams  4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.5 Design of Sequential Systems  4.6 Solving Larger Sequential Problems

Page  200

4.1 Definitions
 Combinatorial circuit is memoryless.  In a circuit with memory, an output value at tn+1 must be a function not only of the inputs at tn+1 but also of the outputs at tn.  To achieve this, the circuit must have some feedback connections from its outputs to its inputs.

Page  201

A circuit with memory is a combinatorial circuit incorporating some feedback connections.

Feedback and memory devices
 To implement feedback, signals are fed back from outputs to inputs using memory devices.  A memory device stores an output value at time tn so that it can be input to the circuit at tn+1.  But then, output at tn depends on input at tn-1, which in turn depends on tn-2…

The circuit maps input sequences to output sequences
Page  202

Sequential circuit model

 Circuits with memory are called sequential circuits.
x1 z1

Circuit inputs

x2 xn

. . .

Combinatorial circuit

. . .

z2

Circuit outputs

yk

Memory device

Yk

Present state
y1
Page  203

. . .

Next state
Y1

Memory device

Sequential circuit model
 Mealy model:
• X : finite inputs. m inputs: x1,x2...,xm • S : finite states. n states: s1,s2...,sn • Y: finite outputs.l outputs: y1,y2...,yl • Fs: state function. s = Fs(X,S) • Fy : output function. y = Fy(X,S)

 Moore: ~Mealy
• Difference: Fy = Fy(S)

Page  204

Asynchronous/Synchronous sequential circuits
 The timing of the signal in the circuit determine two types of sequential circuits:
– Synchronous – Asynchronous.

Page  205

Synchronous sequential circuits
 In a synchronous sequential circuit, the state can change only at discrete instants of time.  To achieve that, the circuit uses a timing device, called a clock generator, that produce trains of periodic or aperiodic clock pulses.  The clock pulses are input to the memory devices so that they can change state only in response to the arrival of a pulse and only once for each pulse occurrence.

The operation of the circuit is synchronized with the clock pulse input.
Page  206

Asynchronous sequential circuits
 The behavior of an asynchronous sequential circuit depends only on the order in which the inputs change and can be affected at any instant of time.  There is no timing device in asynchronous sequential circuit (unclocked memory).

Page  207

4. Sequential Systems
 4.1 Definitions  4.2 State Tables and Diagrams  4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.5 Design of Sequential Systems  4.6 Solving Larger Sequential Problems

Page  208

State diagram
 Depict graphically the operation of a sequential circuit.
– Mealy state diagram

0/0

0/0

a

0/0

b

1/0

c

0/0

d

1/0

1/1

Page  209

Example of state diagram
 Example: a sequential circuit is used to detect the string “0101” from one input.
1 / 0 0 / 0 0 0 / 0 1 / 0 / 0 0 / 0

A

B
1 / 0

C

D

1

/ 1

Page  210

State diagram
 Depict graphically the operation of a sequential circuit.
– Moore state diagram
1

0 f/1 0 1 e/1

a/0 1

0 b/0 1 c/0

0

1
Page  211

0 d/0

1

State table
 State table presents in a tabular form the same information contained in the state diagram.
– Mealy state table – Moore state table

Page  212

Mealy state table
0/0 0/0

PS: Present State NS: Next State
PS x=0 a b c d b b d b NS x=1 a c a c Output (z) x=0 0 0 0 0 x=1 0 0 0 1

a

0/0

b

1/0

c

0/0

d

1/0

1/1

PS a b c d

NS/Output (z) x=0 b/0 b/0 d/0 b/0 x=1 a/0 c/0 a/0 c/1

k memory devices => 2k rows n circuit inputs => NS portion contains 2n columns Page  213 Output portion also contains 2n columns

Moore state table

1

PS x=0 a b c d e f b b d d f f

NS x=1 a c c e e a

Output z 0 0 0 0 1 1
1

0 f/1 0 e/1

a/0 1

0 b/0 1 c/0

0

1

0 d/0

1

0

The output portion always contains a single column. The entry at the intersection of any row with the output column indicates the output values corresponding to the PS associated with that row.
Page  214

Incompletely specified Mealy state table
 Two inputs: x1,x2  A single output: z

PS 00 a b c d e f
Page  215

NS/Output (z) 01 c/1 -/f/1 -/f/0 -/11 b/-/-/e/d/1 c/1 10 e/1 -/-/b/1 a/0 b/0 -/e/0 f/0 a/-/c/0

4. Sequential Systems
 4.1 Definitions  4.2 State Tables and Diagrams  4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.5 Design of Sequential Systems  4.6 Solving Larger Sequential Problems

Page  216

4.3. Latches and Flip-Flops
 Simplest memory devices: Delay element

Yi

ΔT

yi

Yi

yi yi(t+ΔT) = Yi(t) ΔT

In practice, we don’t have to actually insert delay elements because propagation time delays between the inputs and the outputs of the combinatorial part of the circuit provide Page  217 sufficient delay across the feedback loops.

4.3. Latches and Flip-Flops
 Bistable devices:
– Two stable states: • Q=0 : the device is reset (reset state) • Q=1: the device is set (set state) – A bistable device remains in one of two states indefinitely until directed by an input signal to change state. – Two types: • Latch • Flip-flop

Page  218

4.3. Latches and Flip-Flops
 Latch: transparency property:
– Change state when the input values change – The new output state is delayed only by the propagation time delays of the gates between inputs and outputs of the latch. – Used to implement the memory part of asynchronous circuits.

 Flip-flop: no transparency property
– Has a control (triggering) input, called clock. – The state change only in response to a transition of a clock pulse at clock input. – Used to implement memory part of synchronous circuits

Page  219

SR Latch
 Two inputs: S (set), R (reset)  Two complementary outputs: Q, Q’
S Q
S R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 -

Current state
0 0

R

Q’

Next state

S

Q

0 0 1

R

Q'

1 1 1

Indeterminate

Page  220

Q = (R+Q’)’ Q’= (S+Q)’

SR Latch

S

Q

R

Q’

S 0 0 1 1

R 0 1 0 1

Q+ Q 0 1 Indeterminate

S

Q

R

Q'

Equivalent characteristic table

SR=’00’ => Output no change A logic ‘1’ at inputs can change outputs’ states => active-HIGH latch
Page  221

SR Latch

S

Q

S

Q

R

Q’

R

Q’

S

Q

Q S

R

Q'

R Q'

active-HIGH SR Latch

active-LOW SR Latch

Page  222

SR Latch
 Timing chart (NOR implementation)

S

Q

S R

R

Q'

Q Q
set reset set reset

Page  223

SR Latch
 Timing chart (NAND implementation)

Q S

S R

R Q'

Q Q
set reset set reset

Page  224

SR Latch

R

Q

Q 0

Q+ 0 1 0 1

S 0 1 0 -

R 0 1 0

S

0 1 1

Circuit showing feedback

Excitation table

Q+ = R’Q + R’S SR=0 => Q+ = R’Q + R’S + RS = R’Q + S
for active-HIGH SR Latch
Page  225

D Latch

D

Q

D

S

Q

Q’

R

Q’

Graphic symbol

Implementation using SR Latch
Q Q* 0 1 0 1 D 0 1 0 1

D 0 1

Q* 0 1

0 0 1 1

Equivalent characteristic table
Page  226

Q* = D

Excitation table

Gated Latches

S E R

Q

E: Enable input control The latch will not change state as long as E=0 E=1 SR=10 => Set E=1 SR=01 => Reset

Q’

S

Q

⇒The operation of latch is synchronized with the E input => E: synchronous input A latch with synchronous input is called gated latch.

E

R

Q'

Page  227

Flip-flops
 Latches implement memory part in asynchronous sequential circuits  Flip-flops do the same for synchronous circuits. FF has clock input and changes state synchronously with clock.  Four common types of flip-flops:
– SR – D – JK – T

Page  228

SR flip-flop

S CLK R

Q

S CLK

Q

S CLK

Q

Q

R

Q

R

Q

Positive edge-triggered

Negative edge-triggered

Pulse-triggered (Master-Slave)

 The triangle called dynamic indicator, indicates that the device responds only to an input clock transition from LOW (0) to HIGH (1) => Positive edge-triggered  Appending a small circle to the CLK input indicates that the flip-flop responds only to an input clock transition from HIGH (1) to LOW (0) => Negative edge-triggered
Page  229

SR flip-flop

S CLK R

Q

 The information is entered on the leading edge of the clock pulse, but the flip-flop does change state (the output is postponed) until the trailing edge of the clock pulse.

Q’

Pulse-triggered (Master-Slave)

Difference between Latch and Flip-flop?

Page  230

• The flip-flop can not change state except on the triggering edge of clock pulse => synchronous • Present and next states in a latch are separated In time by gate delays, they are separated by clock periods in a flip-flop.

SR flip-flop

Current state
S 0 0 0 0 1 1 1 1 R Q 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q(t+1) 0 1 0 0 1 1 -

Next state
Q Q(t+1) S 0 0 1 1 R 0 1 0 1 Q(t+1) Q(t) 0 1 Indeterminate 0 0 1 1 0 1 0 1 S 0 1 0 R 0 1 0

Reduced characteristic table Indeterminate

Excitation table

Characteristic table

(S=1  231R=1) is inhibited & Page

Q(t+1) = R’Q(t) + S

Implementation of SR-FF

S CL R Implementation of SR-FF by SR-Latch S CL R
Page  232

Q Q

S   Q SR-latch R   Q

Q Q

SR flip-flop
 Timing chart

S
S CLK R Q Q

R CL Q Q

Page  233

D flip-flop

D CLK

Q

D

S CLK R

Q

CLK

Q’

Q

Positive edge-triggered D flip-flop

Implementation using SR flip-flop

 D flip-flop is useful for storing a single bit

Page  234

D flip-flop

Current state
D 0 0 1 1 Q 0 1 0 1 Q(t+1) 0 0 1 1

Next state

Q Q(t+1) 0 D 0 1 Q(t+1) 0 1 0 1 1 0 1 0 1

D 0 1 0 1

Characteristic table Reduced characteristic table

Excitation table

Q(t+1) = D
Page  235

JK flip-flop

J CLK K

Q

S CLK

Q

Q’

R

Q

Positive edge-triggered JK flip-flop

Implementation using SR flip-flop

 JK = 00 => Q* = Q  JK = 01 => Q* = 0  JK = 10 => Q* = 1  JK = 11 => Q* = not(Q)
Page  236

REMEMBER RESET SET INVERT

JK flip-flop

Current state
J 0 0 0 0 1 1 1 1 K Q 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q(t+1) 0 1 0 0 1 1 1 0

Next state
Q Q(t+1) J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 [Q(t)]’ 0 0 1 1 0 1 0 1 J K

0 1 -

1 0

Reduced characteristic table

Excitation table

Characteristic table
Page  237

Q(t+1) = K’Q + JQ’

Master-Slave flip-flop

 A pulse-triggered flip-flop is a bistable device
– states depend on the values of synchronous inputs at the leading edge of the clock pulse – those states does not change until the trailling edge of the clock pulse.

Page  238

Master-Slave flip-flop

S C R

Master
S E R Q’ Q

Slave
S E R Q’ Q

Q Q’

Master latch works when C=1 Slave latch works when C=0

 A pulse-triggered flip-flop consists of two latches, where one acts as a master and the other acts as a slave => Master-slave flip-flop

Page  239

Edge-Triggered flip-flop
 A edge-triggered flip-flop is a bistable device whose state depends on the synchronous inputs either at the positive edge or at the negative edge of a clock pulse.

Page  240

Edge-Triggered flip-flop

Y1

Q CLK Q
Y2

D Positive edge-triggered D flip-flop
Page  241

Edge-Triggered flip-flop

J Q CLK Q K Positive edge-triggered JK flip-flop
Page  242

Flip-Flop conversions

Each FF can mutually converted How to implement y-FF by using x-FF (1) Prepare expanded state table of y-FF (2) Prepare excitation table of x-FF (3) Combine (1) and (2) (4) Calculate logic function for each input of x-ff
combinatorial circuit

input of y-FF

a  Q x-FF CL    b Q

Q Q

Page  243

CL

Flip-Flop conversions
 Example: Implement T-FF using SR-FF

SR-FF S 0 0 0 0 1 1 1 1
Page  244

T-FF Q+ 0 1 0 0 1 1 T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0

R 0 0 1 1 0 0 1 1

Q 0 1 0 1 0 1 0 1

Expanded state table shows the state transition by the input

Flip-Flop conversions
 Example: Implement T-FF using SR-FF
expanded state table excitation table

SR-FF

S 0 0 0 0 1 1 1 1
Page  245

R 0 0 1 1 0 0 1 1

Q 0 1 0 1 0 1 0 1

Q+ 0 1 0 0 1 1 -

state       input Q    Q+    S    R 0 0 0 0 1 1 0 1 0 0 1 1 1 0 Excitation table shows the input value corresponding to the state transition

Flip-Flop conversions
 Example: Implement T-FF using SR-FF

T-FF T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0

excitation table state     input Q    Q+    T 0 0 0 0 1 1 1 0 1 1 1 0

Page  246

Flip-Flop conversions
 Example: Implement T-FF using SR-FF
expanded state table of T-FF T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0

excitation table of SR-FF

state       input Q    Q+    S    R 0 0 0 0 1 1 0 1 0 0 1 Page  247 1 1 0

T 0 0 1 1

Q 0 1 0 1

Q+ S R 0   0 1 - 0 1 1 0 0 0 1

Flip-Flop conversions

 Example: Implement T-FF using SR-FF T 0 0 1 1 Q 0 1 0 1 Q+ S R 0   0 1 - 0 1 1 0 0 0 1 Q 0 1 0 - 0 0 1 1 T Q 0 1 0 0 1 1 0

T

Karnaugh Map of R
S Q T Q Q

Karnaugh Map of S

R=TQ

S=TQ

CL
R Q

Calculate logic function for FF input

Page  248

CL

Flip-Flop conversions

 Example: Implement D flip-flop using JK FF
Q+ D Q 0 0 0 0 0 1 1 1 0 1 1 1 expanded state table of D-FF excitation table of JK-FF

state     input Q    Q+    J K 0 0 0 0 1 1 1 0 - 1 Page  249 1 1 - 0

D 0 0 1 1

Q 0 1 0 1

Q+ J K 0   0 0 - 1 1 1 1 - 0

Flip-Flop conversions

 Example: Implement D flip-flop using JK FF D 0 0 1 1 Q 0 1 0 1 Q+ J K 0   0 0 - 1 1 1 1 - 0 Q 0 1 0 0 1 1 D Q 0 1 0 - 1 - 0 1

D

Karnaugh Map of J
J Q D
Page  250

Karnaugh Map of K

Q Q

J=D

K=D

CL

CL K Q

4. Sequential Systems
 4.1 Definitions  4.2 State Tables and Diagrams  4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.5 Design of Sequential Systems  4.6 Solving Larger Sequential Problems

Page  251

Flip flop excitation equation
 Flip Flop excitation equation express each synchronous input of each flip-flop as a function of the present state and the inputs of the circuit.  These Boolean functions are derived directly from the combinational part of the circuit.

Page  252

Analysis procedure of sequential circuits
 S1. Find excitation equations, and output equations.  S2. Establish state table.  S3. Establish state diagram.

Page  253

Example1: A D flip-flop Moore model circuit
x

D1

~ 1PR 1D 1Q

q1

D2

~ 1PR 1D 1Q

q2 z

1CLK

~ 1Q

1CLK

~ 1Q

~ 1CLR

~ 1CLR

Cl ock

 Excitation equations:
– D1 = q1q2’ + xq1’ – D2 = xq1

 Output equations:
Page  254

Since output is only a function of state z=q2’, and not directly of input, this is Moore model

– z = q2’

Example1: A D flip-flop Moore model circuit
q1* = d1 = q1q2’ + xq1’ q2* = d2 = xq1
State table
0

00 1

q1q2 00 01 10 11
Page  255

q1*q2* x=0 00 00 10 00 x=1 10 10 11 01

z
0

1 0
10 1

1 0 1 0
01 0

1

1
11 0

0

1

State diagram

Example2: A JK flip-flop Moore model circuit
z

x

~ 1PR 1J 1CLK 1K ~ 1Q ~ 1CLR 1Q

A

~ 1PR 1J 1CLK 1K ~ 1Q ~ 1CLR 1Q

B

Cl ock

 Excitation equations:
– JA = x KA = xB’ – JB = KB = x + A’

 Output equations:
Page  256

Since output is only a function of state z=A+B, and not directly of input, this is Moore model

– z=A+B

Example2: A JK flip-flop Moore model circuit
A* = A’JA + AKA= A’x+AxB’ B* = B’JB + BKB = B’(x+A’) + B(x+A’)’ State table
0 0
00 0

AB 00 01 10 11
Page  257

A*B* x=0 01 00 10 11 x=1 11 10 01 10

1

z
01 1

11 1

0

0 1 1 1
1

1

1

10 1

0

State diagram

Example2: A JK flip-flop Moore model circuit

Page  258

Example3: A D flip-flop Mealy model circuit
x

z

~ 1PR 1D 1Q

q1

~ 1PR 1D 1Q

q2

1CLK

~ 1Q

1CLK

~ 1Q

~ 1CLR

~ 1CLR

Cl ock

 Excitation equations:
– d1 = xq1 + xq2 – d2 = xq1’q2’

 Output equations:
Page  259

Since output is a function of both present input and state z=xq1, this is Mealy model

– z = xq1

Example3: A D flip-flop Mealy model circuit
0/0

q1* = d1 = xq1 + xq2 q2* = d2 = xq1’q2’
1/0

0/0
00 11

q 00 01 10 11
Page  260

q*

z
01

0/0 0/0 1/1

x=0 x=1 x=0 x=1
10

00 00 00 00

01 10 10 10

0 0 0 0

0 0 1 Notice that: 1

1/0 1/1

1. State 11 is never reached, this example really only has 3 states. 2. Whenever there is a 0 input, we return to state 00.

Example3: A D flip-flop Mealy model circuit
 Mealy timing trace: x q1 q2 0 ? ? 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 0

z

0

0

0

0

0

0

1

1

0

0

0

Page  261

Example3: A D flip-flop Mealy model circuit

Page  262

4. Sequential Systems
 4.1 Definitions  4.2 State Tables and Diagrams  4.3 Latches and Flip Flops  4.4 Analysis of Sequential Systems  4.5 Design of Sequential Systems  4.6 Solving Larger Sequential Problems

Page  263

Design Procedure for Sequential Systems
 S1. From a word description, determine what needs to be stored in memory, that is, what are the possible states.  S2. If necessary, code the inputs and outputs in binary.  S3. Derive a state table or state diagram to describe the behavior of the system.  S4. Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states.  S5. Choose a state assignment, that is, code the states in binary.  S6. Choose a flip flop type and derive the flip flop input maps or tables.  S7. Produce the logic equation and draw a block diagram.

Page  264

Example1: Design sync sequential circuit using JK
 Design a synchronous sequential circuit using JK flip-flop. The circuit has one input x, one output y. Output is 1 when receiving a string 0101 in input, otherwhile y=0.
Use Mealy model
x=0101011..

System
y=0001010..

A: wait for first 0 B: had 0, wait for 1 C: had 01, wait for 0 D: had 010, wait for 1

1/0 0/0

0/0 0/0

0/0

A

B 1/0

C

D 1/1

1/0
Page  265

Example1: Design sync sequential circuit using JK
Use two state variables q1q2 to encode states in binary
q10

1

q2

x0 S A B C D B,0 B,0 D,0 B,0

1
A,0 C,0 A,0 C,1

0 1

A B

C D
q1q2

x0 00 01 10 11 01,0 01,0 11,0 01,0
Q1Q2

1
00,0 10,0 00,0 10,1
Q1Q2

State table
Page  266

State table after assignment

Example1: Design sync sequential circuit using JK

x0
q1 q2

1
01,0 01,0 01,0 11,0 00,0 10,0 10,1 00,0

q 0

q* J 0 1 0 1 0 1 -

K 1 0 x 0
J 1 K1 J2K2

00 01 11 10

0 1 1

Application table

q1q2

1 J1K1 01-0 -1
J 2 K2

q1*q2*

00 01 11 10

00-1 -0

1-0 -0 1-

0-1 -1 0-

Excitation table
Page  267

Example1: Design sync sequential circuit using JK

Minimization for J1
x q1q2 00 01 11 10 0 0 0 1

q1q2 J1K1

x 0
J2K2 J1K1

1 J2 K2 0-1 -1 0-

00
0 1 -

00-1 -0

1-0 -0 1-

01-0 -1

01 11 10

Excitation equations:

J1 = xq2

J2 = x
Page  268

K2 = x

K 1 = xq 2 + q 2 x

Output equation:

y = xq1q2

Ex 1: Design sync sequential circuit using JK

x

1

J2 CLK K2

q2

&

&
J1 q1

y

CLK q2

=1

K1

q1

CLOCK

Page  269

Ex 2: Design sync sequential circuit using JK
 Design a synchronous sequential circuit using JK flip-flop. The circuit has one input x, one output y. Output is 1 when receiving a string 0111 in input, otherwhile y=0.

Page  270

Ex 3: Design sync sequential circuit using JK
 Design a synchronous up/down counter using JK with one input x. If x=0 the circuit counts up from 0 to 3 and repeat, if x=1 the circuit counts down from 3 downto 0 and repeat.

Page  271

Design Procedure for Sequential Systems
 S1. From a word description, determine what needs to be stored in memory, that is, what are the possible states.  S2. If necessary, code the inputs and outputs in binary.  S3. Derive a state table or state diagram to describe the behavior of the system.  S4. Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states.  S5. Choose a state assignment, that is, code the states in binary.  S6. Choose a flip flop type and derive the flip flop input maps or tables.  S7. Produce the logic equation and draw a block diagram.

Page  272

S4. State reduction
 State transition diagram may include redundancy. State reduction technique aims to simplify sequential circuit by reducing redundancy of the state transition diagram.  Equivalence:
– two states are equivalent if output sequences are the same when the same input sequence is given

 Method 1: Procedure to get equivalent states  Method 2: Reduction of incompletely specified state table

Page  273

State reduction
 Examples:

0/0 B 0/0 0/0 D 1/1

A 1/0 C 1/1 0/0 1/0 1/0 F E 0/0 0/0 0/0 D B 1/1 1/1 0/0 1/0 AF 1/0 E 0/0 C

0/0 1/0

0/0 1/0

unify A and F
Page  274

A and F have the same output and transition state for the same input

State reduction
 Examples:

B 0/0 0/0 D 1/1 1/1

C 0/0 1/0 AF 1/0 E 0/0

B 0/0

0/0 1/1 1/0

C 0/0 1/1 DE 0/0

0/0 1/0

AF

1/0

unify D and E
D and E have the same output and transition state for the same input
Page  275

State reduction
 Examples:

B 0/0

0/0 1/1 1/0

C 0/0 1/1 DE 0/0 0/0 1/0 AF

BC 0/0 1/1 DE 0/0

AF

1/0

1/0

unify B and C

Page  276

State reduction

current state A B C D E F

next state 0 B D E D E B 1 C E D F F C 0 0 0 0 0 0 0

output 1 0 1 1 0 0 0 output 0 0 0 0 1 0 1 0

current state AF B C D E

next state 0 1 B C D E E D D AF E AF

output 0 0 0 0 0 0 1 0 1 1 0 0

current next state state 0 1 AF BC BC BC DE DE DE DE AF
Page  277

current next state state 0 1 AF B C B DE DE C DE DE DE DE AF

output 0 0 0 0 0 1 0 1 1 0

State reduction
 Method 1: Procedure to get equivalent states
– (1) Find multiple states that have the same output with the same input, and treat them as a set of state S1 (s1,s2,…) – (2) Rewrite state transition table by using the set of state. – (3) If the next state of the member of the set are different,the set includes nonequivalent state. Then divide the nonequivalent set and iterate (2)

Page  278

Example of method 1 (1/4)
 Reduce the state of the state transition diagram

0/0

1/0

a
1/0 0/0

b
1/0 1/1

f
0/1 0/1

c
Page  279

0/1 1/1

e
1/1 0/1

current state a b c d e f

0 a d a f d e

next state 1 b c b e c a

output 0 0 1 0 1 1 1 1 0 1 0 1 1 0

d

Example of method 1 (2/4)
current state a b c d e f next state 1 b c b e c a output 0 0 1 0 1 1 1 1 0 1 0 1 1 0 (b,e) and d are not equivakent hence, divide S2 into S2 and S4 S1 S2 S4 S3 a : S1,S2 equivalent c : S1,S2 b : S4,S1 equivalent e : S4,S1 d : S3,S2 f : S2,S1

0 a d a f d e

(1) Find a set of state with the same output S1 (a,c) S2 (b,d,e) S3 (f)

(2) Rewrite next state by using set of state S1 S2 S3 a : S1,S2 c : S1,S2 b : S2,S1 d : S3,S2 e : S2,S1 f : S2,S1

Page  280

Example of method 1 (3/4)
(2) Rewrite state transition table
current state a b c d e f next state 0 1 a b d c a b f e d c e a output 0 0 1 0 1 1 1 1 0 1 0 1 1 0

S1 S2 S4 S3

a : S1,S2 c : S1,S2 b : S4,S1 e : S4,S1 d : S3,S2 f : S2,S1

current state S1 S2 S4 Page  281 S3

next state 0 1 S1 S2 S4 S1 S3 S2 S2 S1

output 0 0 1 1 1 1 0 1 1 0

Example of method 1 (4/4)

Generate state transition diagram
0/0

1/0

a
1/0 0/0

current state S1 S2 S4 S3

next state 0 1 S1 S2 S4 S1 S3 S2 S2 S1

output 0 0 1 1 1 1 0 1 1 0

0/0

b
1/1

f
0/1 0/1 1/1 1/0

c

0/1 1/1

1
0/1

1/0

e
1/1 0/1

2
1/1

3
0/1

d
Page  282

0/1

4

State reduction
 Method 2: Reduction of incompletely specified state table
Incompletely specified: don’t care appears in the next state and output – 1: Find non compatible pairs – 2: Find compatible set that doesn’t involve non compatible pairs – 3: Obtain maximum compatible set – 4: Calculate minimum closed set – 5: Generate reduced state transition table

Page  283

compatible pair: for every input, output are the same

Example of method 2 (1/5)

Implication table
current state a b c d e f next state output input X1X0 input X1X0
00 01 10 11 00 01 10 11

d e a a d

e b b c

b e f -

a e d e

0 1 1

1 0 -

0 0 0 1

0 0 0

b de c × ae d be × de ad e be ae ○ ef bf f × de × × ad ae bc a b c d e 1:fill in × at incompatible pair 2: fill in conditions to be compatible

a set of not compatible pairs (a,c) (a,f) (b,d) (c,f) (d,f)
Page  284

Example of method 2 (2/5)

Decompose state set by non compatible pairs (a,c) (a,f) (b,d) (c,f) (d,f) (a,b,c,d,e,f) (a,c) (a,b,d,e,f) (a,f) (a,b,d,e) (b,d) (b,d,e,f) (b,d) (b,c,d,e,f) (b,d) (b,c,e,f) (c,d,e,f)

(c,f) (c,f) (a,b,e) (a,d,e) (b,e,f) (d,e,f) (b,c,e) (b,e,f) (c,d,e) (d,e,f) (d,f) remove duplicated node remove pair involved to (d,e) (e,f) other node
Page  285

Maximum compatible set is (a,b,e),(a,d,e),(b,e,f),(b,c,e),(c,d,e)

Example of method 2 (3/5)

Maximum compatible set C1:(a,b,e) C2:(a,d,e) C3:(b,e,f) C4:(b,c,e) C5:(c,d,e)

Logic function to represent each set involved a: C1+C2 b: C1+C3+C4 c: C4+C5 d: C2+C5 e: C1+C2+C4+C5 f: C3

Minimum closed set is a subset of maximum compatible set that involves all the state axbxcxdxexf = 1 (C1+C2)(C1+C3+C4)(C4+C5)(C2+C5)(C1+C2+C4+C5)C3 =(C1+C2C3+C2C4)(C2C4+C5) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4)C3 =C1C3C5+C2C3C5+C2C3C4
Page  286

hence (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) are candidates for minimum closed set

Example of method 2 (4/5)

C1:(a,b,e) C2:(a,d,e) C3:(b,e,f) C4:(b,c,e) C5:(c,d,e)

candidate for minimum closed set: (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) check state transition of each candidate by using Implication table C1→(d,e)(a,d),(b,e),(b,f),(a,e) →(a,d,e)(b,e,f) →C1,C3 C2 →(b,e),(a,d),(b,e),(b,f),(e,f) →(b,e,f)(a,d) →C3,C2 C3→(a,e),(d,e),(a,d),(b,c) →(a,d,e)(b,c) →C2,C4 C4→(a,e) →(C1|C2) C5→(d,e),(e,f) →(C2|C5),C3 C2,C3,C4 is closed

Implication table b de c × ae d be × de ad e be ae ○ ef bf f × de × × ad ae bc Page  287 a b c d e

Example of method 2 (5/5)

C2:(a,d,e),C3:(b,e,f),C4:(b,c,e) are used current state a b c d e f next state output input X1X0 inputX1X0
00 01 10 11 00 01 10 11

current state C2 C3 C4

next state input X1X0
00 01 10 11

output input X1X0
00 01 10 11

d e a a d

e b b c

b e f -

a e d e

0 1 1

1 0 -

0 0 0 1

0 0 0

C2 C3 C3 C2 0 0 0 0 C2 C4 C3 C2 1 1 1 0 C2 C4 C3 C2 1 1 0 0

Reduced State Transition Table

Page  288

Design Procedure for Sequential Systems
 S1. From a word description, determine what needs to be stored in memory, that is, what are the possible states.  S2. If necessary, code the inputs and outputs in binary.  S3. Derive a state table or state diagram to describe the behavior of the system.  S4. Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states.  S5. Choose a state assignment, that is, code the states in binary.  S6. Choose a flip flop type and derive the flip flop input maps or tables.  S7. Produce the logic equation and draw a block diagram.

Page  289

State assignment
 State assignment is to encode the state table into binary notation, the result is a transition table that combines nextstate table and the output table.  Better state allocation results in an easy logic function for input of FF.  SP (Substitution Property): indicator for good state allocation. C C1 a b c d a b c d divide state into blocks so that the next state of the same block exists in the same block C2 state is allocated to distinguish blocks of SP

Page  290

State assignment
current state q1 q2 q3 q4 q5 q6 current state u 1u2 u 3 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 next state input   X 0 q2 q3 q1 q5 q6 q4

1 q4 q6 q5 q2 q1 q3

block 1 (q1,q2,q3) block 2 (q4,q5,q6) This partition is SP The first bit is used to distinguish the blocks.

0 u u u 3+ 1+2+ 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0

next state input   X

1 u u2+ 3+ 1+ u 1 1 1 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0

Page  291

Chapter 5. Hardware Design Languages

Page  292

Problems
 Problem 1: Design a synchronous up/down counter using JK with one input x. If x=0 the circuit counts up from 0 to 3 and repeat, if x=1 the circuit counts down from 3 downto 0 and repeat.  Problem 2: Design a synchronous counter using JK with one input x. The circuit counts from 0 to 13 then repeat.  Problem 3:

Page  293

Problems for sequential circuit design
 Textbook:  Chapter 6: 6.5
– 7a,b,c,d, – 8a,b,c,d – 9a,b,c,d

 Chapter 7: 7.6
– 4,5,6,8,9,11,13,15

Page  294

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