You are on page 1of 38

DESIGN OF A

MINI STEREO
DIGITAL AUDIO
PROCESSOR
(MSDAP)

_______________________________________
Chintan Modi(chm130430)
Ujas Patel(unp130030)

OBJECTIVES

Implement a Mini Stereo Digital Audio Processor (MSDAP) with


o

Dual channel inputs (Left and Right)

Sleep and Normal mode of operation

Serial I/O interface

Implement the design in VHDL/Verilog using behavioral and RTL


modeling.

Write a test bench to verify the complete functionality of the design.

Synthesize the RTL code using design vision.

Layout generation using IC compiler.

Report the area, timing and power.

GENERAL DESCRIPTION

FIR digital filtering is used for MSDAP which perform following


convolution:

where:

x(n) and y(n) are input and output audio sequences


h(k) are filter coefficients with the filter order N.

The basic principle involved is shifting operation in order to divide a


number by 2. This saves the hardware cost.

Where u is a function of x. In the first step, by checking the value of r, the


no of x values that should be included in the u function is determined.
Where the k value in x(n-k) is determined from the value of the u table.

FEATURES
A system clock (Sclk) of 26.88MHzand a data
clock (Dclk) of 768 KHz is used.
16 bit audio input and 40 bit audio output.
Supports dual channel serial inputs with the
Dclk.
Supports dual channel serial outputs with the
Sclk.
Automatic sleep mode when 800 consecutive zero
inputs are obtained.

ASIC DESIGN FLOW

MSDAP ABSTRACT VIEW

FINITE STATE MACHINE

OPERATION MODES OF MSDAP

State 0 (Initialization):
FSM enters this state when Start signal is high.
The system initializes.
Remains in this state as long as the Start is high.
When the initialization process is complete, the chip enters state 1.

State 1 (waiting to receive rj):

Remains in state 1 waiting for the rj values to appear on the input channels.

When the Frame signal is set high, the chip enters state 2.

State 2 (reading rj):


rj values from both channels are read by the chip and stored in corresponding rj
memory.
InReady signal remains high in State 2.
Once all the rj values have been read, the chip enters state 3.

OPERATION MODES OF MSDAP

State 3 (waiting to receive coefficients):


Remains in state 3 while waiting for the coefficients to appear on the input
channels.
When Frame signal is set high, chip enters state 4.

State 4 (reading coefficients):


Coefficient values from both channels are read by the chip and stored in corresponding coefficient
memory.
InReady signal remains high in State 4.
Once all the coefficient values have been read, the chip enters state 5.

State 5 (waiting to receive data):


Remains in state 5 while waiting for the data samples to appear on the input channels.
When the Frame signal is set high, the chip enters state 6.
If Reset_n is detected low, the chip enters state 7.

OPERATION MODES OF MSDAP

State 6 (working): input samples are read by the chip and stored in memory.
The convolution is computed and output data is sent out serially once the computation is completed.
InReady signal remains high during this state.
If Reset_n is detected low, the chip enters state 7.
If the chip detects 800 consecutive zero samples at both the input channels simultaneously, it enters
state 8.

State 7(clearing):
Data memory is cleared.
Once the clearing process is completed, the chip goes to state 5.
As long as the Reset_n is low, the chip remains in this state.

State 8 (sleeping):
If 800 consecutive zeros are detected on both the input channels chip enters this state.
If a non-zero sample is detected on any of the input channels, the chip transitions to state 6.
If Reset_n is detected low, the chip enters state 7.

TOP VIEW OF MSDAP

TOP VIEW OF MSDAP(CNT..)

Input audio samples are converted to the digital format by the


Analog-to-Digital Converter (ADC) and sent to the controller.

MSDAP receives the control signals and the input data from the
controller.

MSDAP block processes the data and sends the output samples to
the controller block.

Digital-to-Analog Converter (DAC) converts the digital output back


to analog format.

SYSTEM SPECIFICATION
Pin

Sclk

Dclk

Frequency
System clock is operating at a frequency of 26.88MHz.
During this clock Chip implements Linear Convolution .

Data clock runs at a frequency of 768kHz. During this


clock the data inputs, rj and coefficients are serially
transmitted to the MSDAP

PIN ASSIGNMENT ON MSDAP CHIP

INPUT PINS
Pin

Pin Number

Description

Sclk

Dclk

Start

15

System clock is operating at a frequency of 26.88MHz. It is the clock


where the state change happens and the output data is transmitted during
this clock. The Convolution is computed during this clock.
Data clock runs at a frequency of 768kHz. During this clock the data
inputs, rj and coefficients are serially transmitted to the MSDAP.
When the Start signal is set high, the chip begins initialization process.

Reset_n

Frame

20

InputL

17

InputR

16

When Reset_n is set low, the chip begins to reset. The outputs, inputs
and counters are set to zero.
Frame is used to align the serial coefficients, input and output samples.
In case of first bit Frame is set high for one Dclk cycle after receiving
the first bit then it is set low.
The left channel coefficients are given through InputL at the negative
edge of Dclk.
The right channel coefficients are given through InputR at the negative
edge of Dclk.

OUTPUT PINS
Pin

Pin Number

Description

InReady

12

OutReady

11

OutputL

OutputR

10

It is set high if the chip is ready to get the inputs.


Acknowledgement signal to receive the input by the
MSDAP chip.
If the MSDAP chip is transmitting the outputs, OutReady
is set high else it is set low.
It is used to transmit the Left Channel outputs in a serial
format. Sign bit(Bit 0) is transmitted first and Bit
39(LSB) is transmitted last.
It is used to transmit the Right Channel outputs in a serial
format.

SIGNAL FORMAT
Sign Bit

MSB

Time Slots

LSB

13-bits

15

Input Data
Unused Bits

MSB coefficient data LSB

0 to 7

8 to 15

RJ Data
Unused Bits

MSB

Rj data

LSB

0 to 7

9 to 14

15

Coefficients Data

INPUT CONVERSION
Input Data received as 16 bit is converted to 40 bits.
16 zeros are padded at the end of Input data, as filter
order is 256(maximum 16 shifts possible)
Sign Extension is done on First 8 bits
For Coeffecients, Last 8 bits indicate the maginitude and
the 9th bit is the sign bit.Other bits are discarded
For Rj, Last 8 bits indicate the magnitude and rest are
discarded

TIMING DIAGRAM FOR INPUT

TIMING DIAGRAM FOR INPUT(CNT..)

The first bit (MSB) is received when the Frame is detected high on
the rising edge of the Dclk.

Hence the Frame signal denotes the beginning of the input data
stream.

After the first bit is received the Frame goes low. InReady is high
during this time denoting that the chip is ready to receive data.

TIMING DIAGRAM FOR OUTPUT

TIMING DIAGRAM FOR


OUTPUT(CNT..)

OutReady is set high when the chip is ready to transmit data.

OutputL/OutputR carries the serial output samples.

Output is sent at rising edge of Sclk.

Output frame starts with the rising edge of the Frame and lasts 40
Sclk cycles.

SIPO (SERIAL IN PARALLEL OUT)


UNIT
Signals

Description

InputL/R

Carries the left/right channel


coefficients and data values

Frame

Input data is read when the


frame signal becomes high

Dclk

The input is read on the rising


edge of dclk

state

It will send signal for readrj or


readuj

data/R

16 bit data to be written into


memory.

trigrj

Starts reading for values of rj

triguj

Starts reading for values of


coefficient

readrj

16 bit data ready to be written


into rj memory

readuj

Bit data ready to be written


into coefficient memory

MEMORY
Signals

Description

Sclk

Operations take place on the rising edge of


sclk

Start

Initialization of registers take place

data/R

16 bit data to be written from SIPO

readrj

Signal from SIPO to be ready to write rj data

Readuj

Signal from SIPO to be ready to write


coefficient data

state

Indication of data on data/R is whether rj or


coefficient

storerj

Indication that all rj datas has been written


into memory

storeuj

Indication that all coefficients has benn


written into memory

addr_rj/rjR

Provides the read address of rj to the


memory

addr_uj/ujR

Provides the coefficient address to the


memory

Rj/rjR_data

16 bit rj/rjr data from memory

uj/ujR_data

16 bit uj/ujr data from memory

PISO (PARALLEL IN SERIAL OUT)


UNIT
Signals

Description

Sclk

All operations take


place on the falling
edge of sclk

Frame

Input data is read when


the frame signal
becomes high

OutReady

High when the chip is


ready to transmit
output samples

OutputL/R Serial output


outflag

Signal from ALU


indicating that output
is ready to send

outY/YR

Output from ALU

DATA MEMORY
Signals

Description

state

It is from controller indicating


changes in state and switches
between sleeping state and compute
state.

Frame

Input data is read when the frame


signal becomes high

Dclk

Input is read on the rising edge of


dclk

trigx

Signal from controller to starts


reading input samples

readx

Indication that data is ready to be


written

tempX/XR

It is used in ALU

InputL/R

Carries input samples

sleepof

In sleeping mode, if any of input


sample is non zero, it indicates
controller to change state from state
8 to state 6.

CONTROLLER
Signals

Description

Start

When start is high, the chip initializes

InReady

Set high by MSDAP

Sclk

All operation takes place on rising edge of sclk

Frame

Frame is set high for one dclk cycle when the


first bit of the input sample or coefficients arrive,
otherwise it is low

Reset_n

Reset_n is made low, the chip resets

Sleepof

From input memory to indicate to turn of


sleeping mode

trigrj

Trigger rj memory

triguj

Trigger coefficient memory

storerj

Indication that all rj datas has been written into


memory

storeuj

Indication that all coefficients has benn written


into memory

trigsleep

Trigger sleep mode

trigx

Trigger input memory

resetflag

Signal from controller to other modules for reset

algoinit

To initialize ALU unit

ALU
Signals

Description

Sclk

Computations take place on the


rising edge of sclk

Start

Initializes the ALU unit

q/qR

Address of rj/rjr for


computation

b/bR

Address of coefficients for


computation

outflag

It is signal to SIPO indicating


that output is ready to send

Y/YR

Output from shifter which is


passed to PISO

trigsleep

It is from controller to put alu


in sleep mode

algoinit

It is from controller to initialize


ALU

resetflag

Reset signal from controller

WAVEFORMS (STATE 0,1,2)

State0 is an initialization phase. When the initialization process is completed, the MSDAP enters State 1.

MSDAP starts reading the Rj values and the InReady signal continues to remain high in State 2. One by
one bit is read of first Rj on data. If all Rj values have been loaded, the MSDAP enters State 3

WAVEFORMS (STATE 3,4)

In State 3 the MSDAP is waiting to receive the coefficients. In this state InReady is set high. If Frame signal
is detected to be high, MSDAP enters State 4.

In State 4, the chip starts reading the coefficients. In this the InReady signal remains high.

WAVEFORMS (STATE 5,6)

Once all the coefficients have been loaded, the MSDAP enters State 5.

In State 5, the MSDAP is waiting to receive the data. In this state InReady is set high. If Frame is detected
to be high, the chip enters State 6. It receives the data

WAVEFORMS (STATE 7,7->5)

If reset_n is low State 6 goes to State 7

If reset_n is high State 7 goes to State 5

TIMING, AREA & CELL REPORTS

DESIGN RULE AND CPU STATISTICS


REPORT

FINAL CHIP LAYOUT

CONCLUSION

A mini stereo digital audio processor (MSDAP) has been


implemented

Timing reports show no timing violations

Layout of the complete design has been implemented using IC


compiler

A summary of the results is shown in the table below

REFERENCE
1)

Dian Zhou, Modern ASIC Design. Beijing, China: Science Press,


2011.

2)

Zhangnong Jiang, A Mini Stereo Digital Audio Processor


(MSDAP), Proc. ICASSP89, pp. 1239-1242, 1989

3)

Tala,Deepak.Design and Tool Flow. Retrieved from


http://www.asic-world.com/verilog/design_flow1.html

4)

Michael Smith, Application-specific integrated circuits.


Boston,USA: Addison-Wesley Longman Publishing Co., Inc.,
1997.

5)

http://www.emmelmann.org/Library/Tutorials/docs/verilog_ref_gu
ide/vlog_ref_top.html

THANK YOU