SOI TECHNOLOGY

-Silicon on Insulator

Guide :
M.Ravindra
Asst.Prof of ECE Dept.

By:
V.Priyanka
(14L31D7011)

CONTENTS
Introduction
History of SOI Technology
What is SOI
Why SOI
SOI fabrication
Types of SOI
Floating body effect
History effect
Mechanism of SOI
Advantages
Applications
Conclusion
References

INTRODUCTION
SOI is the semiconductor wafer technology.
It is one of several manufacturing strategies employed to allow the

miniaturization of microelectronic devices.

The performance and power goals for certain applications in these

advanced nodes couldnt be achieved with conventional silicon (bulk

CMOS) process.
SOI fabrication process helps in achieving greater performance and

offers less power consumption compared to the Bulk Process.

HISTORY OF SOI TECHNOLOGY

SOI technology was first introduced in the 1970s as a substrate technology

for military or space applications.

In 1993 Honeywell started product development of SOI to support
commercial aircraft electronic engine controls.
Increasing demand for high performance, low power and low area among
micro-electronic device led to its invention.

Leakage currents in bulk mosfets

pn junction leakage current

Sub threshold leakage

Hot carrier effect

GIDL

Tunneling into & through

gate oxide

Reduction of leakage currents using SOI

WHAT IS SOI ???

It is the latest fabrication technique.
Silicon on insulator (SOI) works by placing a thin, insulating layer, such

as silicon oxide or glass, between a thin layer of silicon and the silicon
substrate.

WHY SOI ???

To enhance the performance

Higher speed.
Less power consumption.
Easier fabrication.
More electronic devices can be fabricated on same chip (30% more than
bulk).
It reduces parasitic capacitance when compared to bulk silicon wafer.

SOI STRUCTURE
Silicon junctions are formed in the active layer and the buried oxide layer

(BOX) is sandwiched in between the active layer and substrate .

The conduction is confined to thin layer of silicon, thereby reducing the loss
due to bulk conduction.

SOI FABRICATION

SOI requires fewer mask and ion implantation steps for the elimination of
well & field isolation implements.
The fabrication processes involved in the SOI technology are
SIMOX (Separation by implantation of oxygen)
Smart-cut SOI Technology
BESOI Bond and Etch-back SOI
SOS Silicon-on-Sapphire

SIMOX (Separation by Implantation of oxygen)

Basic SIMOX process involves ion implantation and annealing at

temperatures in excess of 1300 oC.

Ion Implantation: Ion of a material is accelerated in an electric field and
impact into the other solid is called Ion Implantation technique.
Annealing: It is a heat process whereby a metal is heated to a specific
temperature and then allowed to cool slowly. This softens the metal which
means it can be cut and shaped more easily.

SMART CUT TECHNOLOGY

Smart Cut is a technique used to transfer ultra-thin single crystal layer of wafer

substrate material (such as silicon) onto another surface.

BESOI (Bond and etch back SOI)

It is done after formation of SOI wafer.
It is the technique of fabrication of

semiconductor device or interconnection of

electronic device to form desired circuit.
In BESOI technology, the key processing
step is the etch-stop layer.
Etching: It is used micro fabrication to
chemically remove layers from the surface of
a wafer during manufacturing.

SOS (Silicon on Sapphire)

An epitaxial growth of the Si film is formed

on the sapphire substrate.

The condition of the deposited Si film at this
time will show a lot of crystallization defects.
Next Si ions are implanted inside the Si film,
this destroys the crystallization of the Si film
and converts it into an amorphous condition.
A heat treatment is conducted in an oxidizing
atmosphere, to form an Si film with fewer
flaws by recrystallizing the amorphous Si film.
The oxide film is then removed to obtain the
desired Si film.

TYPES OF SOI

PD-SOI
According to sheet resistance R=L/A
According to ohms law I=V/R
For an n-type PDSOI MOSFET the sandwiched p-type film between the

gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region
can't cover the whole p region.
So to some extent PDSOI behaves like bulk MOSFET.

FLOATING BODY EFFECT

In Silicon-On-Insulator process technology, the source, body, and drain

regions of transistors are insulated from the substrate.

The body of each transistor is typically left unconnected and that results in
floating body.
The floating body can get freely charged/discharged due to the transients
(Switching) and this condition affects threshold voltage (Vt) and many other
device characteristics.

HISTORY EFFECT IN PD-SOI

The body of the NMOS or PMOS Transistors in the SOI is floating instead

of tie to Ground (NMOS) or VDD (PMOS) as in bulk CMOS.

This floating body can change the MOS Transistor Threshold voltage due to
differences in the Body voltages.
This could cause variation in the circuit
delay and mismatch between two identical
devices.
As the SOI circuit switches, the Body Voltages
of the switching transistors will change from
their previous steady state condition.
This is called the History Effect.

FD-SOI
For an n-type FDSOI MOSFET the sandwiched p-type film between the

gate oxide (GOX) and buried oxide (BOX) is small. So the depletion region
covers the whole p region.
The length of the substrate is further reduced and the ultra thin body avoids
a floating body effect in PDSOI.
A technology designed to operate this way is called a fully depleted SOI
technology.

MECHANISM OF SOI
1.low junction capacitance

SOI layer reduces the parasitic junction capacitance of the switch, so that it

operates faster.
The thicker the Sio2 oxide, the smaller the parasitic capacitance.

Switching speed and Power consumption in SOI

Switching Speed: Reducing the junction capacitance can significantly

improve switching speed

T=RC
C total switching capacitance of the node which includes gate
capacitance, source/drain junction capacitance and interconnect
capacitance
Power consumption: Reducing the junction capacitance can reduce the
power consumption. Power consumption can be characterized by
P=CV2/f

2.Latch up effect
Latch-up refers to unintentional

activation of parasitic devices.

Latch is the generation of low

impedance path in CMOS chips

between the power supply and the
ground rails due to interaction of
pnp and npn bipolar transistors.
Due to which there will be
continuous conduction of current in
the circuit.
Ic=Ib

Latch up elimination in SOI

The buried oxide layer that insulates SOI devices from bulk substrate acts
as a capacitor dielectric and blocks DC signals from coupling between
devices.
SOI has no wells into the substrate and therefore has no Latch up or
leakage paths.

3. Self heating:
Due to thermal isolation of substrate through the buried insulator in an SOI

transistor, removal of excess heat generated by the Joule effect through the
device is less efficient than in bulk which leads to substantial elevation of
device temperature
This happens only when there is logic switching in the device.
The device heats up to 50 to 150C due to the relatively low thermal
conductivity of the buried oxide.
This increase in device temperature leads to a reduction in mobility and
current drive. Thus degrading the device performance over a period of time.

4.Elimination of substrate noise

With the increased integration of Digital and Analog circuits on the same die,

Substrate Noise issue is dominant in the Bulk process.

The digital noise can effect the sensitive analog circuits.

In SOI technology the Buried Oxide layer acts a dieelectric barrier and it helps reducing the Substrate
Noise.

5. False switching:
A low gain parasitic bipolar transistor on every floating body SOI FET

transistors.
Bipolar transistor is in parallel with the FET transistor and can cause false
switching to the off FET transistor.

Differentiating bulk devices from PDSOI & FDSOI

SOI DEVICES (Z RAM)

Zero capacitance RAM works only with silicon on insulator.
Z-RAM relies on the floating body effect.
The floating body effect causes a variable capacitance to appear between

the bottom of the tub and the underlying substrate, and was a problem in
circuit designs.
The same effect, however, allows a DRAM-like cell to be built without
adding a separate capacitor, the floating body effect taking the place of the
conventional capacitor.

a) Dram

b) Z-ram

READ & WRITE OPERATION IN Z-RAM

Read operation is performed by triggering the intrinsic bipolar transistor.

The bipolar transistor is on when the cell state is 1, and it is off when
the cell state is 0.
To write a 1 the injected electrons of the source are accelerated and
generate electron hole pairs by impact ionization at the body drain pn
junction.

a) Read operation

b) Write operation

ADVANTAGES

Suitable for high-energy radiation environments.

Parasitic capacitances of SOI devices are much smaller.
No latch-up.
Elimination of substrate noise.
Less temperature sensitivity.

LIMITATIONS OF SOI

Major bottleneck is high manufacturing

costs of the wafer.
Floating-body effects prevent extensive
usage of SOI.
Floating body causes the History Effect
Self-heating

APPLICATIONS
The application of SOI devices are in daily use products in markets such as :
Mobile multimedia (Smartphones, Tablets, Netbooks ),
Imaging (Digital Camera, Camcorders),
Home multimedia (Set Top Box, TV, Blu-Ray),
Automotive Infotainment

CONCLUSION
SOI reduces the leakage currents and the parasitic capacitances compared to

the CMOS bulk process.

SOI provides higher performance at equivalent VDD, Reduced Temperature
sensitivity, Latch up Elimination ,Small transistor saves lot of Area and
power savings .
These advantages simplify fabrication steps, improve density and reduce
parasitic capacitance.

REFERENCES
SOI Implementation guide by Nghia Phan (Prominent Reference)
Synopsys Solvnet Article on SOI
D. Bol, R. Ambroise, C. Roda Neve, J.-P. Raskin and D. Flandre, "Wide-

Band Simulation and Characterization of Digital Substrate Noise in SOI

Technology", IEEE International SOI Conference 2007, pp.133-134,
2007.d.o.i.: 10.1109/SOI.2007.4357888
UCL SOI Consortium by D. Flandre
J.P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, Second
Edition

QUERIES ???

THANK YOU .