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Sequential Circuits

Some Slides from:

U.C. Berkeley,

Alan Mishchenko,

Mike Miller,

Gaetano Borriello

Reduce number of latches assign minimum-length encoding only as the logarithm of the number of states 2. Increase the number of unassigned states codes heuristic to improve state-assignment and logic-optimization .State Minimization Goal : identify and remove redundant states (states which can not be observed from the FSM I/O behavior) Why : 1.

states transition to same or equivalent states Algorithm Sketch 1.Algorithmic State Minimization Goal – identify and combine states that have equivalent behavior Equivalent States: Same output For all input combinations. Repeat (3) until no further partitioning is required states left in the same set are equivalent Polynomial time procedure . Initially partition set based on output behavior 3. Place all states in one set 2. Successively partition resulting subsets based on next state transitions 4.

State Minimization Definition Completely-specified state machine two states are equivalent if outputs are identical for all input combinations Next states are equivalent for all input combinations equivalence of states is an equivalence relation which partitions the states into disjoint equivalence classes Incompletely specified state machines .

Define the partitions so that all states in a partition transition into the same nextstate partition (under corresponding inputs) .Classical State Minimization 1. Partition states based on input output values asserted in the state 2.

Basic Principle of State Minimization for Completely Specified Machines Procedure (fast) for lazy students Any two states of Moore Machine that have the same output and transit to the same states under the same input symbols are equivalent and can be combined This step is repeated until no more equivalent states exist SZ SY X SA X X X SC States SZ and SZ are equivalent and are combined to one state by pointing all arows that go to SY to state SZ and removing SY with its all arrows .

Procedure (fast) for lazy students (for Mealy machines) Any two states of Mealy Machine that have the same output for the same input symbol and transit to the same states under the same input symbols are equivalent and can be combined This step is repeated until no more equivalent states exist SY SZ X Z SA X X Z Z X SC Z SZ X Z SA X Z SC States SZ and SZ are equivalent and are combined to one state by pointing all arows that go to SY to state SZ and removing SY with its all arrows .

Classical State Minimization Algorithm Only for Completely specified Machines 1. Partition the set of internal states based on input output values asserted in the state 2. Define the partitions so that all states in a partition transition into the same next-state partition (under corresponding inputs) .

C.F)(H) B and F go to D States A.B.Example (FSM in Kiss format) Ex : 0A 1A 0B 1B 0C 1C 0D 1D 0E 1E 0F 1F 0G 1G 0H 1H B0 C0 D0 E0 F0 A0 H0 G0 B0 C0 D0 E0 F1 A0 H0 A0 G has other input-output response than other states (A.F.C.H) (G) (A.H)(G)(D) D has other input-output response than other states because it goes to G which is known to be nonequivalent state-goes to red and blue groups (A.B. C and E can be combined to one state States B and F can be combined to one state Please check this using triangular table You can also marke each new group with a new symbol and check transitions to thus marked groups .D.F.E.E.E)(G)(D)(B.C.

F.B.E.F)(H) .D.H)(G)(D)(B.H)(G)(D) (A.E.C.B.E.F) (A.C.E)(G)(D)(B.H)(G) (A.C.C.F.Example of partition based minimization Ex : 0A 1A 0B 1B 0C 1C 0D 1D 0E 1E 0F 1F 0G 1G 0H 1H B0 C0 D0 E0 F0 A0 H0 G0 B0 C0 D0 E0 F1 A0 H0 A0 (A.

State Minimization Example Sequence Detector for 010 or 110 0/0 0/0 S3 S1 S0 Input Sequence Next State Present StateX=0 X=1 Output X=0 X=1 Reset 0 1 00 01 10 11 S0 S1 S2 S3 S4 S5 S6 0 0 0 0 1 0 1 1/0 1/0 0/0 S4 S5 S2 1/0 S6 1/0 1/0 1/0 1/0 0/0 0/1 0/0 0/1 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 0 0 0 0 0 0 0 .

Method of Successive Partitions Input Sequence Next State Present StateX=0 X=1 Output X=0 X=1 Reset 0 1 00 01 10 11 S0 S1 S2 S3 S4 S5 S6 0 0 0 0 1 0 1 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 0 0 0 0 0 0 0 ( S0 S1 S2 S3 S4 S5 S6 ) S1 is equivalent to S2 ( S0 S1 S2 S3 S5 ) ( S4 S6 ) S3 is equivalent to S5 ( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 ) S4 is equivalent to S6 ( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 ) .

Minimized FSM State minimized sequence detector for 010 or 110 Input Sequence Present State Reset 0+1 X0 X1 S0 S1' S3' S4' S0 X/0 0/0 S1’ 1/0 S4’ S3’ X/0 0/1 1/0 S1' S3' S0 S0 Next State X=0 S1' S4' S0 S0 Output X=1 X=0 0 0 0 1 0 0 0 0 X= .

More Complex State Minimization Multiple input exampleinputs here 00 00 S0 [1] 10 10 01 11 00 S2 [1] 10 S4 [1] S3 [0] 10 01 11 10 10 00 11 00 01 01 01 11 S1 [0] 11 S5 01 [0] 00 11 present state S0 S1 S2 S3 S4 S5 00 S0 S0 S1 S1 S0 S1 next state 01 10 11 S1 S2 S3 S3 S1 S4 S3 S2 S4 S0 S4 S5 S1 S2 S5 S4 S0 S5 symbolic state transition table output 1 0 1 0 1 0 .

Implication Chart Method Cross out incompatible states based on outputs Then cross out more cells if indexed chart entries are already crossed out present state S0' S1 S2 S3' S1 S0-S1 S2 S1-S3 S2-S2 S3-S4 S3 S0-S0 S4 S1-S1 S2-S2 S3-S5 S5 S0 S0-S1 S3-S0 S1-S4 S4-S5 S0-S1 S3-S4 S1-S0 S4-S5 S1 S1-S0 S3-S1 S2-S2 S4-S5 S2 00 S0' S0' S1 S1 next state 01 10 11 S1 S2 S3' S3' S1 S3' S3' S2 S0' S0' S0' S3' output 1 0 1 0 minimized state table (S0==S4) (S3==S5) S1-S1 S0-S4 S4-S0 S5-S5 S3 S4 .

g.Minimizing Incompletely Specified FSMs Equivalence of states is transitive when machine is fully specified But its not transitive when don't cares are present e.. state output S0 S1 S2 –0 1– –1 S1 is compatible with both S0 and S2 but S0 and S2 are incompatible No polynomial time algorithm exists for determining best grouping of states into equivalent sets that will yield the smallest number of final states .

outputs 1 when last two input changes from 0 X’ to 1 X Q Q Q Q 00 [0] X’ 01 [1] X X’ 11 [0] X 1 X 0 0 0 1 1 1 – 0 0 1 0 0 1 1 + 1 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 + 0 0 0 0 1 1 1 0 Q1+ = X (Q1 xor Q0) Q0+ = X Q1’ Q0’ .Minimizing States May Not Yield Best Circuit Example: edge detector .

not minimal but cheap and fast X’ X’ 10 [0] X’ 00 [0] X X’ 11 [0] X X 01 [1] X . "Ad hoc" solution .

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