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ECE 301 Digital Electronics

Counters
(Lecture #16)

3-bit Counter: State Diagram


000
111

001

110

010

101

011
100

ECE 301 - Digital Electonics

Counters

Asynchronous Counters
(aka. Ripple Counters)

ECE 301 - Digital Electonics

4-bit (up) Counter

Let each bit in the counter be represented by the output of


a flip-flop.
Count

A3

A2

A1

A0

Count

A3

A2

A1

A0

10

11

12

13

14

15

ECE 301 - Digital Electonics

4-bit (up) Counter: T Flip-Flops

Counter does not


use a common clock.

Asynchronous
Counter

ECE 301 - Digital Electonics

4-bit (up) Counter: T Flip-Flops


Clock
A0
A1
A2
A3
Count

ECE 301 - Digital Electonics

4-bit (up) Counter: D Flip-Flops

Counter does not


use a common clock.

Asynchronous
Counter

ECE 301 - Digital Electonics

Counters

Synchronous Counters

ECE 301 - Digital Electonics

4-bit (up) Counter

As before, let each bit in the counter be represented by the


output of a flip-flop.
Count

Q3

Q2

Q1

Q0

Count

Q3

Q2

Q1

Q0

10

11

12

13

14

15

ECE 301 - Digital Electonics

4-bit (up) Counter: T Flip-Flops


1

Synchronous
Counter

Clock

Q0

Q1

Q2

Q3

Counter uses a common clock.


Clock
Q0
Q1
Q2
Q3
Count

10

ECE 301 - Digital Electonics

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12

13

14

15

10

4-bit (up) Counter: JK Flip-Flops

Synchronous
Counter

Counter uses
a common clock.

ECE 301 - Digital Electonics

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4-bit Counter: D Flip-Flops


Enable

D Q

Q0

How does the XOR gate


function when the Enable
signal is a logic-1?

D Q

Q1

D Q

Q2

D Q

Q3

Q
Output
carry

Clock

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Synchronous Counters

Binary Counter with Parallel Load

ECE 301 - Digital Electonics

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4-bit Counter with Parallel Load


Enable
D0

0
1

D Q

Q0

D1

0
1

D Q

Q1

D2

0
1

D Q

Q2

D3
Is the Load signal
active-high or active-low?

0
1

D Q

Q3

Q
Output
carry

Load
Clock
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4-bit Counter with Parallel Load

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Synchronous Counters

Modulo-6 Counter

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Modulo-6 Counter: D Flip-Flops


Enable
D0
D1
D2
Load
Clock

1
0
0
0

3-bit counter
with Parallel Load

Q0
Q1
Q2

Counter resets to zero


when count reaches six.

Clock

Clock
Q0
Q1
Q2
Count

ECE 301 - Digital Electonics

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Modulo-6 Counter: T Flip-Flops


1

Clock

Q0

Q1

Q2

Counter cleared when


count reaches six.

asynchronous clear signal


Clock
Q0
Q1
Q2
Count 0

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Counters

BCD (Decimal) Counter


(aka. Modulo-10 Counter)

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BCD Counter: State Diagram

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BCD Counter: JK Flip-Flops

Asynchronous
Counter

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BCD Counter: D Flip-Flops

Synchronous
Counter

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Synchronous Counters

Up / Down Counter

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4-bit Up / Down Counter

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Acknowledgments

The slides used in this lecture were taken, with permission,


from those provided by PUBLISHER for
TEXT BOOK NAME (3rd Edition).
They are the property of and are copyrighted by
PUBLISHER.

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