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COUNTER UNIT






Asynchronous up and down counters
Asynchronous modulus counters
Seven segment displays/ BCD coding
Synchronous Counters
Pre-settable Counters
Ring Counters

COUNTERS CHARACTERISTICS
1. MODULUS- number of counts in one cycle
2. Up or down count
3. Asynchronous or synchronous operation
4. Free running or self stopping

ASYNCHRONOUS COUNTERS
•Only LSB flip-flop controlled by the clock input
•Also known as a RIPPLE COUNTER
•Two or more “T” flip-flops interconnected, output
of each flip-flop connected to clock input of the next.
•Modulus- number of stable states in each flip-flop cycle
•Modulus =

2

N

N= number of flip-flops

•Highest number in count =

2

N 1

Q outputs connected to clock input of following flip-flop 3. 4 JK flip-flops in toggle mode. Direction of count can be reversed by complementing each FF’s output or complementing each FF’s input D C D J 1 B C CLK D J 1 A B CLK K 1 C J 1 A CLK K 1 B J 1 K 1 CLK K 1 A . FF D = MSB 4. D do not toggle till receive NGT from proceeding F 5.BUILD A 4 BIT RIPPLE 1. C. FF A = LSB (one with clock input). toggles when input cloc toggles from high to low.all JK inputs tied COUNTER high 2. FF B.

What is the highest count of a four bit counter? 31 .TEST 1. What is the term for the number of counts in one counter cycle? Modulus of the counter 2. How is the modulus determined? 2 N N  number of flip  flops 3. the counter is ____________________? Asynchronous 4. What is the mod number of a counter containing 5 flip-flops? 32 5. Since only the first flip-flop of a ripple counter is controlled by a clock.

CONVERT MOD 8 TO MOD6 C B C J 1 B 1 B CLK C C J 1 A K 1 A CLK K B INPUT CLK A J 1 K 1 CLK master reset 3 FLIP FLOPS 2  MOD 8 HIGHEST COUNT  2  1  7 3 3 0 1 2 3 4 5 6 7 C 0 0 0 0 1 1 1 B 0 0 1 1 0 0 1 A 0 1 0 1 0 1 0 UNSTABLE STATE .PROGRAMMING A RIPPLE COUNTER •Counters may be made to recycle after any desired count by using a gate to reset the counter.

SKIP STEPS 2 AND 3 X N 2.HOW TO BUILD A COUNTER TO GO FROM ZERO TO MOD NUMBER X 1. Connect a NAND gate output to asynchronous clears of all FF 3. Determine which FF’s will be high at count = X Connect the Q outputs of these FF’s to NAND gate inputs . Determine smallest number of FF’s such2that  N IF 2  X .

BUILD A COUNTER THAT COUNTS FROM ZERO TO NINE (X=MOD 10) 1. Determine smallest number of FF’s such2that  N 2  8 and 2  16 3 4 X thus 4 FF’s are required 2. Connect a NAND gate to asynchronous clears of all FF’s 3. Determine which FF’s will be high at count = X Connect the Q outputs of these FF’s to NAND gate inputs 1 1 0 0 D C D J 1 B C CLK D J 1 A B CLK K 1 C J 1 A CLK K 1 B J 1 K 1 CLK K 1 A .

•Stop at desired count: Stop at 1010  1010 2 1 0 D J 1 1 C CLK D J 1 0 B CLK K 1 C J 1 A CLK K 1 B J 1 K 1 CLK K D C B A 1 A .SELF-STOPPING COUNTER •Counters may be made to stop counting after any desired count by using a gate to inhibit the clock.

PROGRAMMING COUNTERS USING JK INPUTS •Counters can be controlled using the JK inputs •Low on JK of 1st FF will cause it to stop toggling on any count •High or low at JK inputs forces counter to skip states 1 1 D J 1 0 C CLK D J 1 0 B CLK K 1 C J 1 A CLK K 1 J CLK B K C D 1 A K .

ASYNCHRONOUS DOWN COUNTER •Direction of count can be reversed by (a) complementing each FF’s output or (b) complementing each FF’s input .

If count starts at decimal 11 and receives seven clock pulses.COUNTER 1. What is the modulus of this counter? 4. what is the new value 12 on10 the counter? 5. What value does the NAND gate reset the value to?2  810 1000 6 3. What is the unstable state of the counter? 1110 2  1410 B A 0V S J Q CP K QN R S J Q CP K QN R D C S J Q CP K QN R S J Q CP K QN R . What is the value PROBLEM of the last usable state before the 13 NAND gate resets 1101 the circuitry? 2 10 2.

QB=1. What is the value PROBLEM of the unstable state. What is the modulus of this counter? 4 1 A +V 0V S J Q CP K QN +V R 2 B 4 C +V +V S J Q CP K QN R S J Q CP K QN R .COUNTER 111 7 1. If QA=1. and 5 clock pulses are applied: QC= 1 QB= 0 QA= 0 4. and QC=0. in decimal? 011  3 2 10 2. At what value does the NAND gate set the counter to? 2 10 3.

IC ASYNCHRONOUS COUNTERS Logic Diagram for 7493 ___ CPo J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R ___ CP1 MR1 MR2 Qo (LSB) Q1 Q2 *All J. K inputs internally connected HIGH Q3 (MSB) .

7493 AS A MOD-16 COUNTER Logic Diagram for 7493 ___ CPo J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R ___ CP1 Qo (LSB) MR1 Q1 Q2 *All J. K inputs internally connected HIGH MR2 ___ CP 7493 MR 1 MR 2 Q 3 Q3 (MSB) ___ CP Q 2 Q 1 Q o F= 10 kHz/16 = 625 Hz 1 10 kHz o .

K inputs internally connected HIGH MR2 ___ CP 7493 MR 1 MR 2 Q 3 Q3 (MSB) ___ CP Q 2 Q 1 Q 1 10 kHz o o F= 10 kHz/10 = 1KHz .TEST Build a MOD 10 counter with a Logic Diagram for 7493 7493 ___ J Q J Q J Q J Q CPo CP K QN R CP K QN R CP K QN R CP K QN R ___ CP1 Qo (LSB) MR1 Q1 Q2 *All J.

. •Also used for dividing a pulse frequency exactly by 10. •Widespread applications where pulses or events are to be counted and the results displayed on a decimal numerical read-out.BCD COUNTER •Binary counter that counts from 0000 to 1001 before it recycles (MOD-10). Cascading BCD counters to count and display from 000 to 999.

MOD-60 COUNTER MOD 6 MOD 10 ___ CP 7493 MR 2 Q 3 f out = f ___ CP Q 2 Q /60 in 1 Q o not used 7493 1 o MR 1 MR 2 Q 3 Q 2 Q 1 Q ___ CP 1 ___ CP o o f in /10 Two 7493s can be combined to produce a MOD-60 Counter f in .

DIGITAL CLOCK .

COUNTERS ASYNCHRONOUS J Q CP K QN R J Q CP K QN R J Q CP K QN R S J Q CP K QN R S S S SYNCHRONOUS D S Q CP QN R D S Q CP QN R D S Q CP QN R D S Q CP QN R .

•Advantage over the ripple counter is speed and accuracy but more co 5V +V 5V Q S J CP QN K R Q S J CP QN K R Q S J CP QN K R Q S J CP QN K R 5V 0V D C B A .SYNCHRONOUS COUNTERS •Two or more FF’s connected as “T” FF’s. •All FF’s in the counter are clocked at the same time.

5V +V Q S J CP QN K R Q S J CP QN K R Q S J CP QN K R Q S J CP QN K R 0V D C B A .SYNCHRONOUS COUNTERS N MOD <2 •A NAND control gate is used to clear the counter before the full count.

SYNCHRONOUS COUNTERS UP/DOWN 0V 5V Q 5V J CP QN K R Q J CP QN K R Q J CP QN K R 5V 0V .

P0. P2 P1 PARALLEL DAT A INPUT S Po 5V +V Q S J CP QN K R Q S J CP QN K R Q S J CP QN K R 5V CLOCK PARALLEL LOAD __ PL . P1.PRESETTABLE COUNTERS Can be preset to any desired count. 2. To operate: 1. Apply desired count to parallel data inputs P2. Apply a low pulse to the parallel load input PL.

. Synchronous Counter (a. Johnson Counter: shift register in which the inverted output of the last FF is connected to the input of the first FF. BCD Counter: counter counts from 0000 to 1001 before it recycles.k.a. Ripple or Serial Counter): each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain.a.k. Up Counter: counter counts from zero to a maximum count.COUNTER TYPES Asynchronous Counter (a. Parallel Counter): all the FF’s in the counter are clocked at the same time. Down Counter: counter counts from a maximum count down to zero. Pre-settable Counter: counter that can be preset to any starting count either synchronously or asynchronously Ring Counter: shift register in which the output of the last FF is connected back to the input of the first FF.

74193 COUNTER MOD-16 PRESETTABLE UP/DOWN COUNTER .

.

RING COUNTER Shift register counter with feedback from Q of last FF back to first RING FF COUNTER input 5V D 5V 0V clk S Q CP QN R D S Q CP QN R D S Q CP QN R D S Q CP QN R .

JOHNSON COUNTER Shift register in which the inverted output of the last FF is fed back to the input of the first FF. 5V D 0V 0V clk S Q CP QN R D S Q CP QN R D S Q CP QN R D S Q CP QN R .

PROGRAM SWITCH X Y 0 0 0 1 1 0 1 1 COUNTER MODE NO COUNT MOD 5 MOD 10 MOD 12 .Lab 18. A PROGRAMMABLE COUNTER COUNTE Design a four-bit counter controlled by two control lines X and Y that behaves according to the truth table.

A PROGRAMMABLE COUNTER COUNTE 5V Q1 CP1 Q2 CP2 D Q S J CP QN K R C Q S J CP QN K R Q B S J CP QN K R A Q S J CP QN K R _ XYAC _ XYBD XYCD X Y X 0 0 1 1 NO COUNT MOD 5 MOD 10 MOD 12 Y 0 1 0 1 COUNTER MODE PROGRAM SWITCH .Lab 18.

RIPPLE COUNTER Binary Output Clock Input 00 1 10 10 1 Pulse 8 1 2 3 4 5 6 7 PS and CLR input All 16 J-K(8) flip-flops This On the 4-bit next counter clockhas pulse states all FFs and are in the will will count toggle from because binary each 0000 will through receive 1111 INACTIVE TOGGLE MODE a H-to-L and then pulsereset one back after to another. Watch Thethe counter counthas ripple a modulus thru theof counter. 0000. 16. .

RIPPLE COUNTER WITH WAVEFORMS Binary Output Clock Input 01 00 10 1 Pulse 5 1 2 3 4 Clock input FFs triggered on 1s output H-to-L pulse. CLK toggles 1s FF. 4s output . 2s output 2s FF toggles 4s FF. 1s FF toggles 2s FF.

Next clock pulse will increment counter for a When count hits 1010 reset to 0000.DECADE COUNTER Binary Output Clock Input 111 0 t nt a u o al c i t i In 11 0 00 11 0 Pulse 8 1 2 3 4 5 6 7 Short negative pulse To clear input of each FF All J & K inputs = 1 All PR inputs = 1 To change mod-16 counter to decade counter: Count is at 1001. . JK FFs to 0 when count hits 1010. short time to 1010 which will activate the NAND gate See added 2-input NAND gate that clears all and reset the counter to 0000. Reset count to 0000 after 1001 (9) count.

DOWN COUNTER 11 0 00 1 t oun c l ia Init t at se 111 y r bina 4 2 1 Pulse 5 3 Changes from Ripple Up Counter are wiring from Q’ outputs (instead of Q outputs) to the CLK input of the next FF. .

SELF-STOPPING DOWN COUNTER 10 0 10 1 unt on The tch coremained Wacount . The 1s FF is in TOGGLE mode when counting (J & K = 1). . The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate when the count decrements to 000. The count stops at 000. Pulse 8000. at binary 2 3 4 Pulse 8 1 5 6 7 This is a 3-bit down counter.

COUNTER USED FOR FREQUENCY DIVISION  8 50 Hz  16 Clock Input 800 Hz 200 Hz 100 Hz  4 400 Hz 2 .

100 ? Hz Hz 400 ? Hz Hz 800 ? Hz Hz 1600 Hz 7493 Counter I wired as a 4-bi binary counter .USING THE 7493 COUNTER IC • Counters are available in IC form. • Either ripple (7493 IC) or synchronous (74192 IC) counters are available.

A(0) A(1) Input Input Inputbinary binary binary0111 1111 0001 A(2) 74HC85 Magnitude Comparator A(3) B(0) B(1) Input Input binary binary 0110 0111 1100 B(2) B(3) A>B HIGH A=B HIGH A<B HIGH .MAGNITUDE COMPARATOR A magnitude comparator is a combinational logic device that compares the value of two binary numbers and responds with one of three outputs (A=B or A>B or A<B).