ANALYSIS OF THE

CIRCUIT
GROUP 4
BSECE-2A
ARANCINA, TRISHA MARIE D.
C H UA , E M E R S O N T.
CONSON, JUSTINE E.
M A G O S , R E Y N A L D O J R . O.
N A R C I S O , A LY SS A J A D E P.
PA LO M A , L A R A H M A R I E P.

Full
Adder

Full Adder (7483)

The 7483 adds two 4-bit binary numbers (A + B)
plus the incoming carry. The binary sum appears on
the sum outputs (S1S4) and outgoing carry (C4)
outputs.
C0+
(A1+B1)+2(A2+B2)+4(A3+B3)+8(A4+B4)=S1+2S2+
4S3+8S4+16C4

Pin Configuration

Logic Diagram

Function Table
INPUT

OUTPUT

CIN

COUT

AND
Gate

AND Gate (7408)

The AND gate is an electronic circuit that gives a
true output (1) only if all its inputs are true. A dot () is
used to show the AND operation i.e. AB. Note that the
dot is sometimes omitted i.e. AB

Pin Configuration

Logic Symbol

Function Table
INPUT

OUTPUT

AB

OR
Gate

OR Gate (7432)
The OR gate is an electronic circuit that gives a true
output (1) if one or more of its inputs are true. A plus
(+) is used to show the OR operation.

Pin Configuration

Logic Symbol

Function Table
INPUT

OUTPUT

A+B

Combinatio
nal circuit

Combinational Circuit

D=A+BC

TRUTH TABLE (Combinational circuit)

INPUT

OUTPUT

Multiplex
er

Multiplexer (74157)
QUAD 2-LINE TO 1-LINE
DATASELECTORS/MULTIPLEXERS
These data selectors/multiplexers contain inverters
and drivers to supply full on-chip data selection to the
four output gates. A separate strobe input is provided.
A 4-bit word is selected from one of two sources and is
routed to the four outputs.

Pin Configuration

Logic Diagram

Function Table
INPUT

OUTPUT

CONTROL

DATA

ENABLE

SELECT

Decoder

Decoder (7447)
The 7447 accepts four lines of BCD (8421) input
data, generates their complements internally and
decodes
the data with seven AND/OR gates having opencollector
outputs to drive indicator segments directly.

Pin Configuration

Logic Diagram

Function Table
DECIMAL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

INPUTS
A2
A1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

a
0
1
0
0
1
0
1
0
0
0
1
1
1
0
1
1

b
0
0
0
0
0
1
1
0
0
0
1
1
0
1
1
1

OUTPUTS
c
d
e
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1

f
0
1
1
1
0
0
0
1
0
0
1
1
0
0
0
1

g
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1

555
Timer

555 Timer

These devices are precision timing circuits

capable of producing accurate time delays or
oscillation. In the time-delay or monostable mode of
operation, the timed interval is controlled by a
single external resistor and capacitor network. In
the astable mode of operation, the frequency and
duty cycle can be controlled independently with two
external resistors and a single external capacitor.

Pin Configuration

Logic Diagram

Function Table
RESET
0
1
1
1

OUTPUT
0
1
0
AS PREVIOUSLY
ESTABLISHED

DISCHARGE SWITCH
ON
OFF
ON
AS PREVIOUSLY
ESTABLISHED

Counter

Counter (7493)
This monolithic counter contains four master-slave
flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for
which the count cycle length is divide-by-eight.
This counter has a gated zero reset.
To use the maximum count length (decade or fourbit binary), the B input is connected to the QA output.
The input count pulses are applied to input A and the
outputs are as described in the appropriate truth
table.

Pin Configuration

Logic Diagram

State Table
CONTROL
R0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

PREVIOUS STATE
QD QC QB QA
XXXX
0000
0001
0010
001 1
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

NEXT STATE
QD QC QB QA
0000
0001
0010
001 1
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000

BLOCK DIAGRAM

FUNCTION OF THE
CIRCUIT

Circuit
1

Circuit 1

Circuit 1

Circuit
2

THE END
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