Digital Design, Mano

© All Rights Reserved

7 views

Digital Design, Mano

© All Rights Reserved

- Scrolling 16*2 led in PIC
- Flip Flop
- Digital Electronics
- ISO-8859-1 Latch Flipflops Reg Counters
- bolum08
- Chap7
- UNIT 5 DLD
- Counters Registers
- Dual Decade Counter; Dual 4-Stage Binary Counter
- Final CEG3155 Fall 2008
- The Following is a List of 7400 Series Digital Logic Integrated Circuits
- Uae
- 08-State Machines 2
- counters and register
- Chapter 6
- Chapter 61688
- Shift Registers
- DF 0 Contents
- Circuits and Ic's Lab Exp 4 & 5
- Assign 10

You are on page 1of 59

6.1 REGISTERS

Register- a group of binary cells suitable for holding binary information.

transferred

Clock=0 ;unchanged

Clear=0 ;clearing the register to all

0s prior to its clocked operation.

Digital System

Digital System

Clock

Clock

unchanged

Load input = 1

; the I inputs are transferred into the

register

Load input = 0

; maintain the content of the register

Digital System

directions

Digital System

information stored in

the source register

Digital System

Serial-Transfer Example

Timing pulse

Shift register A

Shift register B

Serial output of B

Initial value

1011

After T1

After T2

1101

1110

1001

1100

1

0

After T3

After T4

0111

1011

0110

1011

Digital System

0010

For storing sum

Digital System

Operation

the A register ->augend ,the

B register ->addend ,carry ->0

The SO of A and B provide a

pair of significant bits for the FA

Output Q gives the input

carry at z

The shift-right control enables

both registers and the carry flipflop.

The sum bit from S enters the

leftmost flip-flop of A

Input : X,Y(2 significant bits),Z(1 carry bit)

Output : S(sum),C(carry)

Digital System

4-bit adder

A=1011, B=0011

Digital System

10

Serial Adder

xi yi ci

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

ci 1

0

0

0

1

0

1

1

1

si

0

1

1

0

1

0

0

0

(a) Serial adder with D-FF

Digital System

11

Serial Adder

Digital System

12

Serial Adder

Digital System

13

JQ xy

KQ x' y ' ( x y)'

S x y Q

Digital System

Output carry

By k-map

14

Digital System

15

S1, S0 -> 0, 1 ;Shift right

S1, S0 -> 1, 0 ;Shift left

S1, S0 -> 1, 1 ;Parallel

load

Digital System

16

LSB

Digital System

17

Conditions for

Complementing

Count sequence

A3 A2 A1 A0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

Complement A0

Complement A0

Complement A1

Complement A2

Complement A1

A0 will go from 1 to 0

and complement A1

A1 will go from 1 to 0 and

complement A2 ;

A2 will go from 1 to 0 and

complement A3

A0 will go from 1 to 0

and complement A1

Complement A3

and so on

Digital System

18

Digital System

19

Operation

1. Q1 is complemented on the negative edge of every count

pulse.

2. Q2 is complemented if Q8=0 and Q1 goes from 1 to 0. Q2 is

cleared if Q8=1 and Q1 goes from 1 to 0.

3. Q4 is complemented when Q2 goes from 1 to 0.

4 .Q8 is complemented when Q4Q2=11 and Q1 goes from 1 to

0. Q8 is cleared if either Q4 or Q2 is 0 and Q1 goes from 1 to 0

Digital System

20

Digital System

21

Synchronous Counters

Digital System

Binary Counter

Up-Down Binary Counter

BCD Counter

Binary Counter with Parallel Load

Other Counter

22

equal to 1 if the counter is enabled .

The other J and K inputs are

equal to 1 if all previous low-order

bits are equal to 1 and the count is

enabled.

Digital System

23

inputs receive their signals from the

values of the previous normal outputs

of the flip-flops.)

Down input control=1, up input

control=0 ; count down

Up=down=0 ;unchanged state

Up=down=1 ;count up

Digital System

24

TQ1 1

TQ 2 Q ' 8Q1

TQ 4 Q 2Q1

TQ8 Q8Q1 Q 4Q 2Q1

y Q8Q1

Digital System

25

count sequence ,data transfer

Load =0 and count=1 ;count

Load=0 and count=0 ;unchanged

Carry out=1(all flip-flop=1)

Digital System

26

The AND gate detects

the occurrence of state

1001(9) in the output. In

this state, the load input

is enabled and all-0s

input is loaded into

register.

The NAND gate detects

the count of 1010(10) ,

as soon as this count

occurs the register is

cleared.

Digital System

A momentary spike

occurs in output A2 as the

count goes from 1001 to

1010 and immediately to

0000

27

Design Procedure

Step 1. Determine the desired number of bits (FFs) and the

desired counting sequence.

Step 2. Draw the state transition

diagram showing all possible state,

including those that are not part of

the desired counting sequence

for the synchronous counter design

example

Digital System

28

Step 3. Use the state transition diagram to set up a table that lists all

PRESENT states and their NEXT states.

Digital System

29

Step 4. Add a column to this table for each J and K input. For each

PRESENT state, indicate the levels required at each J and K input in

order to produce the transition to the NEXT state.

Digital System

30

Step 5. Design the logic circuits needed to

generate the levels required at each J and K

input.

Fig 7-27 (a) Portion of circuit excitation table

showing JA for each PRESENT state; (b) K map

used to obtain simplified expression for JA.

logic circuits; (b) K maps for the JC and

KC logic circuits.

Digital System

31

Step 6. Implement the final expressions.

Digital System

32

Repeat the counter design sequence with D-FFs.

Digital System

33

Ring Counter

Johnson Counter

Digital System

34

JA B

JB C

JC B '

KA B

KB 1

KC 1

Digital System

35

one flip-flop being set at any

particular time. ; all others are

cleared.

The single bit is shifted from one

flip-flop to the other.

Digital System

36

complement output of the last flipflop connected to the input of the first

flip-flop.

Digital System

37

// Behavioral description of a 4-bit universal shift register

// Fig. 6.7 and Table 6.3

module Shift_Register_4_beh (

// V2001, 2005

output reg

[3: 0]

A_par,

// Register output

input

[3: 0]

I_par,

//

Parallel input

input

s1, s0,

// Select

inputs

MSB_in, LSB_in,

// Serial

inputs

CLK, Clear

// Clock and Clear

);

always @ (posedge CLK, negedge Clear)

// V2001, 2005

if (~Clear) A_par <= 4'b0000;

else

case ({s1, s0})

2'b00: A_par <= A_par;

// No change

2'b01: A_par <= {MSB_in, A_par[3: 1]};

// Shift right

2'b10: A_par <= {A_par[2: 0], LSB_in};

// Shift left

2'b11: A_par <= I_par;

// Parallel load of input

endcase

endmodule

module t_Shift_Register_4_beh ();

reg s1, s0,

// Select inputs

MSB_in, LSB_in,

// Serial inputs

clk, reset_b;

// Clock and Clear

reg [3: 0]

I_par;

// Parallel input

wire [3: 0]

A_par;

// Register output

Shift_Register_4_beh M0 (A_par, I_par,s1, s0, MSB_in, LSB_in, clk,

reset_b);

initial fork

// test reset action load

#3 reset_b = 1;

#4 reset_b = 0;

#9 reset_b = 1;

// test parallel load

#10 I_par = 4'hA;

#10 {s1, s0} = 2'b11;

// test shift right

#30 MSB_in = 1'b0;

#30 {s1, s0} = 2'b01;

// test shift left

#80 LSB_in = 1'b1;

#80 {s1, s0} = 2'b10;

// test circulation of data

#130 {s1, s0} = 2'b11;

#140 {s1, s0} = 2'b00;

// test reset on the fly

#150 reset_b = 1'b0;

#160 reset_b = 1'b1;

#160 {s1, s0} = 2'b11;

join

endmodule

initial begin clk = 0; forever #5 clk = ~clk; end

Digital System

38

`timescale 1ns / 100 ps

module Ripple_Counter_4bit (A3,A2,A1,A0, Count, Reset);

output A3,A2,A1,A0;

input Count,Reset;

//Instantiate complementing flip-flop

Comp_D_flip_flop F0 (A0, Count, Reset);

Comp_D_flip_flop F1 (A1, A0, Reset);

Comp_D_flip_flop F2 (A2, A1, Reset);

Comp_D_flip_flop F3 (A3, A2, Reset);

endmodule

//Complementing flip-flop with delay

//Input to D flip-flop = Q'

module Comp_D_flip_flop (Q, CLK, Reset);

output Q;

input CLK, Reset;

reg Q;

always @ (negedge CLK, posedge Reset)

if (Reset) Q <= 1'b0; else Q <= #2 ~Q;

// else Q <= #2 ~Q;

endmodule

//Stimulus for testing ripple counter

module testcounter;

reg Count;

reg Reset;

wire A0,A1,A2,A3;

//Instantiate ripple counter

Ripple_Counter_4bit M0 (A3, A2, A1, A0, Count, Reset);

always

#5 Count = ~Count;

Digital System

initial

begin

Count = 1'b0;

Reset = 1'b1;

#4 Reset = 1'b0;

end

initial

#200 $finish;

endmodule

39

Digital System

40

D-FF

Digital System

41

JK-FF

Digital System

42

Digital System

43

T-FF

Digital System

44

T-FF

Digital System

45

T-FF

Digital System

46

T flip-flop

Complementing flip-flop

usual for designing binary counters

T flip-flop can be obtained from a JK when inputs J and K are tied together.

If T=0 (J=K=0), the output, Q does not change.

If T=1 (J=K=1), the output, Q is complemented.

D=T

Digital System

Q = TQ+TQ

47

Digital System

48

Digital System

49

Digital System

50

Digital System

51

Signal Flow

MOD Number

MOD number = 2N

, where N is the number of FFs connected in the arrangement of counter.

Frequency Division

Digital System

In any counter, the signal at the output of the last FF (i.e., the MSB)

will have a frequency equal to the input clock frequency divided by

the MOD number of the counter.

52

Digital System

53

Fig 7-4 Waveforms if a three-bit ripple counter illustration the effects of FF propagation

delays for different input pulse frequencies

Digital System

54

Tclock N x tpd

, where N = the number of FFs.

Example.

Suppose 4-bit ripple counter using 74LS112 J-K FF

which has tpLH=16ns and tpHL= 24ns.

then the worst case tpd = tpHL = 24ns.

fmax = 1/(4x24ns) = 10.4 MHz

Digital System

55

Figure 12-9: Typical Timing Diagram for Shift Register of Figure 12-8

Digital System

59

- Scrolling 16*2 led in PICUploaded bymalhiavtarsingh
- Flip FlopUploaded bysujan
- Digital ElectronicsUploaded bykaran007_m
- ISO-8859-1 Latch Flipflops Reg CountersUploaded byYuvraj Pratap Singh
- bolum08Uploaded byjagruthims
- UNIT 5 DLDUploaded byGuru Velmathi
- Counters RegistersUploaded bymdhuq1
- Dual Decade Counter; Dual 4-Stage Binary CounterUploaded bytato20008
- Chap7Uploaded byPei Ing
- Final CEG3155 Fall 2008Uploaded byTrulybored
- The Following is a List of 7400 Series Digital Logic Integrated CircuitsUploaded bymessage4guru
- UaeUploaded byUKhan
- 08-State Machines 2Uploaded byCambalacheMx
- counters and registerUploaded byshivam
- Chapter 6Uploaded bybebo_ha2008
- Chapter 61688Uploaded by55mali
- Shift RegistersUploaded byRajagopalan Sadagopan
- DF 0 ContentsUploaded bydemos2011
- Circuits and Ic's Lab Exp 4 & 5Uploaded bySatya Moorthy
- Assign 10Uploaded byP_lee
- ContentsUploaded byAnonymous CvQTv0
- Testing16.pdfUploaded bydoomachaley
- Digitally Controlled PotentiometersUploaded byJoseGarciaRuiz
- DE-Manual(1)Uploaded byGopinathan M
- Chapter 4 - Flip-flops and Related DevicesUploaded byLoga HS
- 144Uploaded byMarcialCastroLeonidas
- Decodificare_Bistabile_RegistriUploaded byAce Daniel
- BI1109kul8bUploaded byKelvin Yip
- m Qp Digital SystemUploaded byvelmurugan
- CC2510Assignmen05tSolnUploaded bySidney O. Ebot

- Ec2203-Digital Electronics Question BankUploaded byRamadhurai
- LDP-6416Uploaded byMinh Hoàng Nguyễn
- SISO - VerilogUploaded byshabbir470
- HD74LS164PUploaded byRafael Gutierrez
- pseudo codeUploaded byapi-301836448
- List of 7400 Series Integrated CircuitsUploaded bymanikandan
- Chapter 09Uploaded byBrandon Paz
- DigitalUploaded bySreejith Vanery
- Vhdl ExampleUploaded byRabab M Aly
- 14892_ADSP-21160 SHARC DSPUploaded bysbgm
- Spartan-6 FPGA Configurable Logic BlockUploaded byJason Robinson
- Digiatal Electronic LabUploaded byKarthick Karthik
- CS34 Digital Principles and System DesignUploaded bySara Patrick
- An 200 Vinculum-II Scrolling Text Application Using LED Dot Matrix DisplayUploaded byIndra Levyprawira
- Intro LogicUploaded byMaximus Maxis
- dac8563Uploaded byRonnie Wong
- Cm305Uploaded byapi-3853441
- VHDL Code for 4-Bit Shift RegisterUploaded byOsvaldo Hernández
- How to Drive 595 Shift Registers With AVR Hardware SPI JumUploaded byalberto55
- Registers and CountersUploaded byAvijith Chandramouli
- Intro to UartsUploaded bysunny
- freeUploaded byks_pro
- How to Avoid Lock Out ConditionUploaded bySiva Guru
- Esd Lab Record_14122014Uploaded byMohanaprakash Ece
- 1658f.pdfUploaded byMateus Vicente
- 51814615-labviewUploaded byTarun Kumar Sharma
- labviewUploaded byKrishna Rao Vutukuru
- DPSD impUploaded byGanesamoorthy
- digital_registers.pdfUploaded byboymatter
- 74HC_HCT165.pdfUploaded byarturorossi