asic Language Constructs of VHDL

To use a programming language, we first have to learn its syntax and

language constructs
XICAL ELEMENTS AND PROGRAM FORMAT
Lexical elements
The lexical elements are the basic syntactical units in a VHDL program.
They include comments, identifiers, reserved words, numbers,
characters and strings.
Comments: A comment starts with two dashes, --, followed by the
comment text. Anything after the -- symbol in the line will be ignored.
identifiers An identifier is the name of an object in VHDL. The basic
rules to form an identifier are:

The identifier can contain only alphabetic letters, decimal digits and
underscores.
The first character must be a letter
The last character cannot be an underscore.
successive underscores are not allowed.

or example, the following identifiers are valid:

On the other hand, the following identifiers violate one of the rules and
will cause a syntax
error during analysis of the program:
Since VHDL is not case sensitive, the following identifiers
are the same:
Reserved words
Some words are reserved in VHDL to form the basic language constructs.
These reserved words are:

VHDL program format

VHDL is a case-insensitive free-format language, which means that the
letter case does not matter, and "white space" (space, tab and new-line
characters) can be inserted freely between lexical elements.

For example, the VHDL program

is the same as

OBJECTS
An object in VHDL is a named item that holds the value of a specific
data type. There are four kinds of objects: signal, variable, constant
and file. A construct known as alias is somewhat like an object. We do
not discuss the file object in this book since it cannot be synthesized.
Signals
A signal has to be declared in the architecture bodys
declaration section.
For example, the following line declares the a, b and c signals with the
std_logic data type:
Variables
A variable can only be declared and used in a process and is local
to
that
process.
The
syntax
of variable declaration is similar to that of
signal declaration:

Note that no timing information is associated with a variable, and thus

only a value, not a waveform, can be assigned to a variable. Since there
is no delay, the assignment is known
as an immediate assignment and the notion : = is used.

Constants
A constant holds a value that cannot be changed. The syntax of
constant declaration is
The value-expression term specifies the value of the constant. A
simple example is

AIias
Alias is not a data object. It is the alternative name for an existing
object. As a constant, the purpose of an alias is to enhance code
clarity and readability

DATA TYPES
In VHDL, each object has a data type. A data type
is defined by:
A set of values that an object can assume.

A set of operations that can be performed on objects of

this data type.
redefined data types in VHDL

integer: VHDL does not define the exact range of the integer type but
specifies that the minimal range is from -(231 - 1) to 231 - 1, which
corresponds to 32 bits. Two related data types (formally known as
subtypes) are the n a t u r a l and p o s i t i v e data types. The former
includes 0 and the positive numbers and the latter includes only the
positive numbers.
boolean: defined as (false, true).
bit : definedas (O, 1).
bit-vector: defined as a one-dimensional array with elements of
the b i t data type.

a types in the IEEE std-logic-1164 package

d_logic and std_logic_vector data types

To use the new data types, we must include the necessary library and use
statements before the entity declaration:
library ieee ;
use ieee . std _ logic _ 1164 . all ;
The std_logic data type consists of nine possible values, which are shown
in the following list:

These values are interpreted as follows:

Relational Operators for an array

In VHDL, the relational operators can be applied to the one-dimensional
array data type. The two operands must have the same element type,
but their lengths may differ.
For example, all following operations
return true:

Concatenation operator
The concatenation operator, &, is very useful for array
manipulation.
For example, we can shift the elements of the array to the right by two
positions and append two 0s to the front:

or append the MSB to the front (known as an

arithmetic shift):
or rotate the elements to the right by two
positions:
Array aggregate

gned and unsigned data types

For the unsigned data type, the array is interpreted as an unsigned
binary number, with the leftmost element as the MSB of the binary
number.
For the signed data type, the array is interpreted as a signed binary
number in 2s-complement format. The leftmost element is the MSB of
the binary number, which represents the sign of the number.

For
example,
consider
a
4-bit
binary
representation 1100.
It represents the number 12 if it is interpreted as an
unsigned number
epresents -4 if it is interpreted as a signed number.
It may also just represent four independent bits (e.g., four status signals)
if it is interpreted as a collection of bits.
Since the signed and unsigned data types are arrays, their declarations
are similar to that of the std_logic_vector data type, as in

Arrays
Arrays are collections of objects of the same type. They can be onedimensional (1D), two-dimensional (2D), or one-dimensional-by-onedimensional (1Dx1D). They can also be of higher dimensions, but then
they are generally not synthesizable.

Example: 1Dx1D array.

Example: 2D array.

Example: Legal and illegal array assignments.

Data Attributes
The pre-defined, synthesizable data attributes are
the following:

Signal Attributes
Let us consider a signal s. Then:

GENERATE
It allows a section of code to be repeated a
number of times
Its regular form is the FOR / GENERATE construct, with the syntax
shown below. Notice that GENERATE must be labeled.

An irregular form is also available, which uses IF/GENERATE (with an

IF equivalent; recall that originally IF is a sequential statement). Here
ELSE is not allowed. In the same way that IF/GENERATE can be nested
inside FOR/ GENERATE (syntax below), the opposite can also be done.

Example : Vector Shifter

(the original vector is underscored):