IMPLEMENTATION OF AMBA

AHB USING VERILOG

M.GEETHA PRATYUSHA
162052004
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TABLE OF CONTENT
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Advanced High Performance Bus

Features of AHB Bus
Design principles
AMBA 2.0
Components in AHB
AHB Signals
Request / Grant Protocol
Connections for AHP signal

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Advanced High Performance Bus

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AHB is a new generation of AMBA bus which is intended

to address the requirements of high-performance

synthesizable designs.

It is a high-performance system bus that supports multiple

bus masters and provides high-bandwidth operation.

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Features of AHB BUS

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AMBA AHB implements the features required for highperformance, high clock frequency systems
Including:
Burst transfers
Split transactions
Single-cycle bus master handover
Single-clock edge operation
Wider data bus configurations (64/128 bits).

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Design principles
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facilitate right-first-time development of embedded microcontroller

products with one or more CPUs, GPUs or signal processors

Reuse of IP cores, peripheral and system macrocells across diverse IC

processes.
encourage modular system design to improve processor independence,

and the development of reusable peripheral and system IP libraries

minimize silicon infrastructure while supporting high performance and

low power on-chip communication.

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AMBA 2.0
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Components in AHB
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Master

AHB master is able to initiate read and write operations by providing

an address and control information. Only one bus master is allowed
to actively use the bus at any one time.(max. 16)

Slave

AHB slave responds to a read or write operation within a given

address-space range. The bus slave signals back to the active master
the success, failure or waiting of the data transfer.

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Cont
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Arbiter

AHB arbiter ensures that only one bus master at a time is allowed to
initiate data transfers.

Decoder

AHB decoder is used to decode the address of each transfer and

provide a select signal for the slave that is involved in the transfer. A
single centralized decoder is required in all AHB implementations.

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Master Signals
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AHB Arbitration Signals

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Arbitration signals
HGRANTx

Select active bus master

HMASTER[3:0]

Multiplex signals that sent from master to slave

HMASTLOCK

Locked sequence

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AHB Response Signals

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Response signals

HREADY

Transfer done, ready for next transfer

HRESP[1:0]
OKAY transfer complete
ERROR transfer failure(ex: write ROM)
RETRY higher priority master can access bus
SPLIT other master can access bus
HCLK
Clock signal which times all bus transfers
HRESETn
Active Low global reset of master

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Cont
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HRDATA: Read data from the bus slave

HADDR: 32-bit bus address
WDATA: Write data from the processor (provided by the test bench)
RDATA: Read data to the processor (outputted to the test bench)
HSIZE: Indicates the size of transfer,byte,half word or word

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Request / Grant Protocol

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Request
Grant
CPU #1

CPU #2

IP Block #1
IP Block #2
IP Block #3

IP Block #1
IP Block #4

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Request / Grant Protocol

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Before a transaction a master makes a request

to the central arbiter

Eventually the request is granted

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Request / Grant Protocol

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Performance Impact
Then the
transaction
proceeds

Before a transaction a master makes a

request to the central arbiter
Eventually the request is granted

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Connections of AHB masters

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Disadvantages
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Busses that require arbitration:

must route signals to the arbitration logic and back

must find a fair way to share the bus
slaves are not always available => backpressure
difficult to provide performance guarantees...

Still potentially a bandwidth bottleneck

Still doesnt scale well when blocks are added
Multiple outstanding transactions not handled well no ordering information

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18

Thank you

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