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VLSI Design

Dr. T. R. Lenka
Asst. Professor
Deptt. of Electronics & Communication Engg.
National Institute of Technology Silchar

VLSI Design

Introduction to VLSI Design


Historical perspective
Evolution of Microelectronics
Moores Law

VLSI Design

The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
VLSI Design

ENIAC - The first electronic computer (1946)

VLSI Design

The Transistor Revolution

First transistor
Bell Labs, 1948
VLSI Design

The First Integrated Circuits


Bipolar logic
1960s

ECL 3-input Gate


Motorola 1966
VLSI Design

Evolution of Microelectronics
1948

1961

1966

1971

1980

Discrete
Component

SSI

MSI

LSI

VLSI

1
transistor

100

100-1000

1000-20000

>20000

Gates, Counters,
MUX,
FFs
Adders

VLSI Design

8-bit uP,
ROM, RAM

Complex
uP, SoC

Intel 4004 Micro-Processor


1971
1000 transistors
1 MHz operation

VLSI Design

Intel Pentium (IV) microprocessor

2002
42 million transistors
3GHz operation

VLSI Design

Moores Law
In

1965, Gordon Moore noted that the density


of transistors on a chip doubles every 24
months.
In

1980 he made another prediction that the


density of transistors on a chip will be doubled
in every 18 months.

VLSI Design

LOG2 OF THE NUMBER OF


COMPONENTS PER INTEGRATED FUNCTION

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Electronics, April 19, 1965.

VLSI Design
1975

1974

1973

1972

1971

1970

1969

1968

1967

1966

1965

1964

1963

1962

1961

1960

1959

Moores Law

Evolution in Complexity

VLSI Design

Transistor Counts
1 Billion
Transistors

K
1,000,000
100,000
10,000
1,000
i386
80286

100
10

i486

Pentium III
Pentium II
Pentium Pro
Pentium

8086
Source: Intel

1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
VLSI Design
Courtesy,
Intel

Moores law in Microprocessors

Transistors (MT)

1000

2X growth in 1.96 years!

100
10

486

P6
Pentium proc

386
286

0.1
8086

8085
Transistors
on Lead Microprocessors double every 2 years
0.01
8080
8008
4004

0.001
1970

1980

1990
Year
Courtesy, Intel

VLSI Design

2000

2010

Die Size Growth


Die size (mm)

100

10
8080
8008
4004

8086
8085

286

386

P6
Pentium
proc
486

~7% growth per year


~2X growth in 10 years

1
1970

1980

1990
Year

2000

2010

Die size grows by 14% to satisfy Moores Law


Courtesy, Intel

VLSI Design

Frequency
Frequency (Mhz)

10000

Doubles every
2 years

1000
100
10

8085

1
0.1
1970

8086 286

386

486

P6
Pentium proc

8080
8008
4004
1980

1990
Year

2000

2010

Lead Microprocessors frequency doubles every 2 years


VLSI Design
Courtesy,
Intel

Power Dissipation
Power (Watts)

100
P6
Pentium proc
10
8086 286
1

8008
4004

486
386

8085
8080

0.1
1971

1974

1978

1985

1992

2000

Year

Lead Microprocessors power continues to increase


VLSI Design
Courtesy,
Intel

Power will be a major problem


100000

18KW
5KW
1.5KW
500W

Power (Watts)

10000
1000
100

Pentium proc

286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power delivery and dissipation will be prohibitive

VLSI Design
Courtesy,
Intel

Power density
Power Density (W/cm2)

10000
1000
100

Rocket
Nozzle
Nuclear
Reactor

8086
10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year

Power density too high to keep junctions at low temp


VLSI Design
Courtesy,
Intel

Not Only Microprocessors


Cell
Phone
Small
Signal RF

Digital Cellular Market


(Phones Shipped)

Power
RF

Power
Management

1996 1997 1998 1999 2000


Units

48M 86M 162M 260M 435M

Analog
Baseband
Digital Baseband
(DSP + MCU)

(data from Texas Instruments)


VLSI Design

Challenges in VLSI Design


Macroscopic Issues

Microscopic Problems

Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse : Portability
Predictability.

Ultra-high speed design


Interconnect
Noise
Reliability, Manufacturability
Power Dissipation
Clock distribution.

VLSI Design

Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But

How to design chips with more and more functions?


Design engineering population does not double every
two years

Hence, a need for more efficient design methods


Exploit different levels of abstraction
VLSI Design

Design Metrics
How

to evaluate performance of a
digital circuit (gate, block, )?

Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function

VLSI Design

Design Abstraction Levels


SYSTEM

MODULE
+
GATE

CIRCUIT

DEVICE
G
S
n+

VLSI Design

D
n+

Silicon Wafer
Single die

Wafer

Going up to 12 (30cm
From http://www.amd.com

VLSI Design

Design Flow

Design Iteration

Design Capture

Behavioral

HDL
HDL

Pre-Layout
Pre-Layout
Simulation
Simulation

Logic
LogicSynthesis
Synthesis

Post-Layout
Post-Layout
Simulation
Simulation
Circuit
CircuitExtraction
Extraction

Floorplanning
Floorplanning
Placement
Placement
Routing
Routing
Tape-out

VLSI Design

Structural or
Gate level

Physical

Integrating Synthesis with


Physical Design
RTL (Timing) Constraints
Physical
PhysicalSynthesis
Synthesis
Macromodules
Fixed netlists

Netlist with
Place-and-Route Info

Place-and-Route
Place-and-Route
Optimization
Optimization
VLSI Design Artwork

Design Methodology

Design process traverses iteratively between three abstractions:


behavior, structure, and geometry
More and more automation for each of these steps
VLSI Design

A Simple Processor

INPUT/OUTPUT

MEMORY

CONTROL

DATAPATH

VLSI Design

A System-on-a-Chip: Example

Courtesy: Philips
VLSI Design

Implementation Choices
Digital Circuit Implementation Approaches

Custom

Semicustom

Cell-based

Standard Cells
Compiled Cells

Array-based

Macro Cells

Pre-diffused
(Gate Arrays)

VLSI Design

Pre-wired
(FPGA's)

The Custom Approach


Intel 4004

VLSI Design
Courtesy
Intel

Transition to Automation and Regular Structures

Intel 4004 (71)

Intel 8080

Intel 8286
VLSI Design
Courtesy
Intel

Intel 8085

Intel 8486

Cell-based Design (or standard cells)

Rows of cells

Feedthrough cell

Logic cell

Routing
channel

Functional
module
(RAM,
multiplier,)

VLSI Design

Routing channel
requirements are
reduced by presence
of more interconnect
layers

Standard Cell The New Generation


Cell-structure
hidden under
interconnect layers

VLSI Design

Standard Cell - Example

3-input NAND cell


(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

VLSI Design

MacroModules

25632 (or 8192 bit) SRAM


Generated by hard-macro module generator

VLSI Design

Soft macros

Soft macros are in synthesizable RTL.


Soft macros are more flexible than firm or hard macros.
Soft macros are not specific to any manufacturing process.
Soft macros have the disadvantage of being somewhat
unpredictable in terms of performance, timing, area, or power.
Soft macros carry greater IP protection risks because RTL
source code is more portable and therefore, less easily
protected than either a netlist or physical layout data.
From the physical design perspective, soft macro is any cell
that has been placed and routed in a placement and routing
tool such as Astro Rail.
Soft macros are editable and can contain standard cells, hard
macros, or other soft macros.

VLSI Design

Firm macros
Firm

macros are in netlist format.


Firm
macros are optimized for
performance/area/power
using
a
specific fabrication technology.
Firm macros are more flexible and
portable than hard macros.
Firm
macros
are
predictive
of
performance and area than soft macros.

VLSI Design

Hard macro

Hard macros are generally in the form of hardware IPs (or we termed it
as hardwre IPs !).
Hard macos are targeted for specific IC manufacturing technology.
Hard macros are block level designs which are silicon tested and
proved.
Hard macros have been optimized for power or area or timing.
In physical design you can only access pins of hard macros unlike soft
macros which allows us to manipulate in different way.
You have freedom to move, rotate, flip but you can't touch anything
inside hard macros.
Very common example of hard macro is memory. It can be any design
which carries dedicated single functionality (in general).. for example it
can be a MP4 decoder.
Be aware of features and characteristics of hard macro before you use it
in your design... other than power, timing and area you also should know
pin properties like sync pin, I/O standards etc
LEF, GDS2 file format allows easy usage of macros in different tools.
VLSI Design

The physical design (backend)


perspective
Hard macro is a block that is generated in a
methodology other than place and route (i.e.
using full custom design methodology) and is
brought into the physical design database (eg.
Milkyway in Synopsys; Volcano in Magma) as a
GDS2 file. (GDS = Graphic Database System)
Synthesis and placement of macros in modern
SoC designs are challenging. EDA tools employ
different algorithms accomplish this task along
with the target of power and area.

VLSI Design

Soft MacroModules

Synopsys DesignCompiler
VLSI Design

Intellectual Property

A Protocol Processor for Wireless


VLSI Design

What are IPs?

Hard macro, firm macro and soft macro are all known
as IP (Intellectual property).
They are optimized for power, area and performance.
They can be purchased and used in your ASIC or
FPGA design implementation flow.
Soft macro is flexible for all type of ASIC
implementation.
Hard macro can be used in pure ASIC design flow, not
in FPGA flow.
Before bying any IP it is very important to evaluate its
advantages and disadvantages over each other,
hardware compatibility such as I/O standards with
your design blocks, reusability for other designs.
VLSI Design

Late-Binding Implementation
Array-based

Pre-diffused
(Gate Arrays)

Pre-wired
(FPGA's)

VLSI Design

Gate Array Sea-of-gates


polysilicon
VD D

rowsof
uncommitted
cells

metal
possible
contact

GND

In 1 In2

In 3 In4

routing
channel

Committed
Cell
(4-input NOR)
Out

VLSI Design

Uncommited
Cell

Sea-of-gates
Random Logic

Memory
Subsystem
LSI Logic LEA300K
(0.6 m CMOS)
VLSI Design
Courtesy
LSI Logic

Prewired Arrays
Classification of prewired arrays (or field-programmable devices):

Based on Programming Technique


Non-volatile EPROM based (EPLD)
RAM based

Programmable Logic Style


Array-Based (EPLD)
Look-up Table

VLSI Design

Based on Programming Technique


Non

Volatile FPGA
(EPLDs)

RAM

Based FPGA

Array logic +
Embedded EPROM

Cell logic +
Embedded RAM

Serial PROM

VLSI Design

Based on implementation of logic


Array

based programmable logic


(PROM, PLA, PAL) Programmable
logic devices (PLDs)
Loss of programming density and performance in
implementing complex functions on a single array
Only implements combinational functions
Very regular structure but high capacitance

Cell

based logic

Multiplexers are used as function generators


Look-up tables (LUT)
VLSI Design

Array-Based Programmable Logic


I5

I4

I3

I2

I1

I0

Programmable
OR array

Programmable AND array

I2

I1

I0

Programmable
OR array

Fixed AND array


O 3O 2O 1O 0

PLA

I3

I5

I4

I3

I2

I1

I0

Fixed OR array

Programmable AND array


O3O2O1O0

PROM
Indicates programmable connection
Indicates fixed connection

VLSI Design

O 3O 2O 1 O 0

PAL

Programming a PROM
1

X2

X1

X0

: programmed node
NA NA f 1 f 0

VLSI Design

Two-Level Logic
Every logic function can be
expressed in sum-of-products
format (AND-OR)

minterm

Inverting format (NORNOR) more effective


VLSI Design

Programmable Logic Array


GND

GND

GND

V DD

GND

GND

GND

GND

V DD

X0

X0

X1

X1

X2

X2

AND-plane

f0

f1

OR-plane

VLSI Design

More Complex PAL


programmable AND arrayi 3
(2 jk)

k macrocells
product
terms

j -wide OR array
D

OUT

j
macrocell
CLK
A

i inputs

i inputs, j minterms/macrocell, k macrocells


VLSI
Design
From
Smith97

Cell Based Design


Mutiplexers

based logic cells


Look-up table based logic cells

VLSI Design

2-input mux as programmable logic block


Configuration
A

0
F

F = AS + BS

VLSI Design

F=

0
0
0
0
X
Y
Y
1
1
1

0
X
Y
Y
0
0
1
0
0
1

0
1
1
X
Y
X
X
X
Y
1

0
X
Y
XY
XY
XY
X+ Y
X
Y
1

Logic Cell of Actel Fuse-Based FPGA


A
B

How to realise XOR gate


by using the logic cell ?

SA

Y
1

C
D

A=1, B=0, C=0, D=1,


SA=SB=In1, S0=S1=In2;

SB
S0
S1

VLSI Design

Memory

Look-up Table Based Logic Cell


Out

ln1 ln2

In

Out

00

00
0

01

10

11

Any complex function can be realised


by using either a bigger size LUT or a
number of LUTs
VLSI Design

LUT-Based Logic Cell


4

C1....C4

H1
G4
G3
G2

Logic
function
of
G1-G4

G1

F3
F2
F1

Logic
function
of
F1-F4

K
CLOCK

SR/H0 EC
Bits
control

Din

Logic
function
of
F,G, H1

F4

DIN/H2

Bypass

F
G
H

D SD Q

G
H

EC RD
1

Y
Bits
control

Din

F
G
H

YQ

D SD Q

Bypass
XQ

EC RD
H
F

1
Multiplexer Controlled
by Configuration Program

Xilinx 4000 Series Configurable Logic Block


VLSI Design

Courtesy Xilinx

Configurable Logic Block


It combines two four-input LUTs feeding a
three-input LUT.
The cell has two FFs whose inputs can be
any of the LUT outputs or an external input.
X any Y outputs of LUTs are used to build
complex combinational functions.
C1-C4 can be used as inputs or SR or for
clock enable

VLSI Design

Programmable Interconnection
M

Interconnect
Point

Programmed interconnection

Input/output pin

Cell

Horizontal

tracks

Vertical tracks

VLSI Design

Mesh-based Interconnect Network


Switch Box

CLB

CLB

CLB
Connect Box

CLB

CLB

CLB
Interconnect
Point

CLB

CLB

Design
CourtesyVLSI
Dehon
and Wawrzyniek

Transistor Implementation of Mesh

Design
CourtesyVLSI
Dehon
and Wawrzyniek

EPLD Block Diagram


Macrocell

Primary inputs

Courtesy Altera
VLSI Design

Xilinx 4000 Interconnect Architecture

CLB

12

Quad

Single

Double

Long

2
3

12

Quad

Long

Global

Long

Clock

Double Single Global

2
Carry

Direct

Clock Chain Connect

VLSI Design
Courtesy
Xilinx

Direct

Connect

Long

Design at a crossroad

500 k Gates FPGA


MultiSpectral
+ 1 Gbit DRAM
RAM
Imager
Preprocessing
64 SIMD Processor
Array + SRAM
Image Conditioning
100 GOPS

Analog

System-on-a-Chip

C
system
+2 Gbit
DRAM
Recognition

VLSI Design

Embedded applications
where cost, performance,
and energy are the real
issues!
DSP and control intensive
Mixed-mode
Combines programmable
and application-specific
modules
Software plays crucial role

Addressing the Design Complexity Issue


Architecture Reuse
Reuse comes in generations
Generation

Reuse element

Status

1st

Standard cells

Well established

2nd

IP blocks

Being introduced

3rd

Architecture

Emerging

4th

IC

Early research

VLSI Design

Heterogeneous Programmable Platforms


FPGA Fabric

Embedded memories
Embedded PowerPc

Hardwired multipliers

Xilinx Vertex-II Pro


Courtesy Xilinx

High-speed I/O
VLSI Design

Comparison of the approaches


Design metrics FPGA
Cost
Cheap
Performance Poor

ASIC
Expensive

Flexibility

Good

Limited

Programming
by customer

Full
Limited
hardware
change
VLSI Design

Good in terms of
speed, area and
power consumption

VLSI Testing

VLSI Design

Gravity of the testing problem

N inputs

N inputs
K Outputs

M stage

Combinational

K Outputs

M stage
Register

Sequential
VLSI Design