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vco

The output frequency varies from 1 to 2 (the


required tuning range) as the control voltage, Vcont,
goes from V1 to V2. The slope of the characteristic,
KVCO, is called the gain or sensitivity of the VCO

In order to vary the frequency of an LC oscillator, the


resonance frequency of its tank(s) must be varied.
Since it is difficult to vary the inductance electronically,
we only vary the capacitance by means of a varactor.
MOS varactors are more commonly used than pn
junctions, especially in low-voltage design. A regular
MOSFET exhibits a voltagedependent
gate capacitance

Cascade of two tuned amplifiers 360 degree phase shift

Mos varactor added to change frequency of oscillation


the gates of the varactors are tied to the oscillator nodes and the
source/drain/n-well terminals to Vcont.

the average voltage across each varactor varies from


VDD to zero as Vcont goes from zero to VDD, thus
creating a monotonic decrease in their capacitance.
The oscillation frequency can thus be expressed as

The tuning range obtained from the CV characteristic may prove


prohibitively narrow, particularly because the capacitance range
corresponding to negative VGS (for Vcont > VDD) remains unused.
We must therefore seek oscillator topologies that allow both
positive and negative (average) voltages across the varactors,
utilizing almost the entire range from Cmin to Cmax.
We select the transistor dimensions such that the CM level is
Approximately equal to VDD/2. Consequently, as Vcont varies from
0 toVDD, the gate-source voltage of the varactors, VGS,var, goes
from + VDD/2 to VDD/2, sweeping almost the entire capacitance
range from Cmin to Cmax

PLL implementation
PHASE DETECTOR
Loop filter
VCO
If the loop is locked, the input and output frequencies are equal, the
PD generates repetitive pulses,
The loop filter extracts the average level, and the VCO senses this
level so as to operate at the required frequency.
: the PD input is a phase quantity, the PD output and the LPF output
are
voltage quantities, and the VCO output is a phase quantity.

The input and output have equal frequencies but a finite


phase difference, 1, and the PD generates pulses
whose width is equal to 1. These pulses are low-pass
filtered to produce the dc voltage that enables the VCO
to operate at a frequency equal to the input frequency,
1. The residual disturbance on the control line is called
the ripple.

Fequency multiplication
The M circuit is a counter that generates one output pulse
for every M input pulses .
in the locked condition, F = in and hence out = Min.
The divide ratio, M, is also called the modulus

The PLL can also synthesize frequencies: if the divider


modulus changes by 1, the output frequency changes by in.

Modern RF synthesizers rarely employ the simple PLL


studied here. This is for two reasons
tight relation between the loop stability () and the corner
frequency of the low-pass filter. the ripple on the control
line modulates the VCO frequency and must be suppressed
by choosing a low value for LPF. But, a small LPF leads
to a less stable loop.
Second, the simple PLL suffers from a limited acquisition
range, e.g., if the VCO frequency and the input frequency
are very different at the startup, the loop may never
acquire lock

the problem of limited acquisition


range.
this limitation arises because phase detectors produce
little information if they sense unequal frequencies at
their inputs.
the acquisition range can be widened if a frequency
detector is added to the loop.
Thus, it is desirable to seek a circuit that operates as an
FD if its input frequencies are not equal and as a PD if
they are.
Such a circuit is called a phase/frequency detector
(PFD).

PFD

Phase/Frequency detector
The circuit produces two outputs, QA and QB, and operates based on
the following principles:
(1) a rising edge on A yields a rising edge on QA (if QA is low),
and (2) a rising edge on B resets QA (if QA is high).
if A > B, then QA produces pulses while QB remains at zero.
Conversely, if B > A, then positive pulses appear at QB and QA =
0.
On the other hand, if A = B, the circuit generates pulses at either
QA or QB with a width equal to the phase difference between A and B.
Thus, the average value of QA QB represents the frequency or
phase difference.

at least three logical states are necessary:


QA = QB = 0;
QA = 0, QB = 1;
and QA = 1, QB = 0.
to avoid dependence of the output upon the duty cycle
of the inputs, the circuit should be realized as an edgetriggered sequential machine

Design of pfd
If the PFD is in state 0, then a transition on A takes it to
state I, where QA = 1, QB = 0. The circuit remains in
this state until a transition occurs on B,upon which the
PFD returns to state 0.

At the beginning of a transient, the PFD acts as a


frequency detector, pushing the VCO frequency toward
the input frequency. After the two are sufficiently close,
the PFD operates as a phase detector, bringing the loop
into phase lock.
The dc content of QA QB is extracted by the low-pass
filters

trade-off between the damping


factor and the corner frequency of
the loop filter

Charge pumps solves this issue


A charge pump sinks or sources current for a limited
period of time.
A pulse of width T on Up turns S1 on for T seconds,
allowing I1 to
charge C1. Consequently, Vout goes up by an amount
equal to T I1/C1. Similarly, a pulse on Down yields a
drop in Vout.

A leads B, then QA produces pulses and Vout continues to


rise. A key point here is that an arbitrarily small (constant)
phase difference between A and B still turns one switch on
albeit brieflythereby charging or discharging C1 and
driving Vout toward + or albeit slowly.
In other words, the circuit exhibits an infinite gain, where
the gain is defined as the final value of Vout divided by
the input phase difference.
From another perspective, the PFD/CP/C1 cascade
produces a ramp-like output in response to a constant
phase difference, displaying the
behavior of an integrator

Charge pump pll


a finite error would lead to an unbounded value for
Vcont.

Tyransfer function of PFD/CP/C1

Type 2 pll since oltf has two poles


two poles on the j axis, indicating an oscillatory
system
integrators becomes lossy the system can be stabilized.
This can be accomplished by inserting a resistor in
series with C1.
The resulting structure is chargepump pll

PLL-Based Modulation
In addition to frequency synthesis, PLLs can also
perform modulation.
transmitter architectures that merge the modulation
and frequency synthesis functions
FSK and GMSK modulation can be realized by means of
a VCO that senses the binary data
Open loop modulation

the filter smoothes the time-domain transitions to some


extent, thereby reducing the required bandwidth.
The principal issue here is the poor definition of the
carrier frequency: the VCO center frequency drifts with
time and temperature with no bound
One remedy is to phase-lock the
VCO periodically to a reference so as to reset its center
frequency

In loop modulation
such a system first disables the baseband data path and
enables the PLL, allowing fout to settle to NfREF. Next,
the PLL is disabled and xBB(t) is applied to the VCO.

requires periodic idle times during the communication to


phase-lock the VCO, a serious drawback.
Also, the output signal bandwidth depends on KVCO, a poorlycontrolled parameter.
Moreover, the free-running VCO frequency may shift from NfREF
due to a change in its load capacitance or supply voltage. if the
power amplifier is ramped at the beginning of transmission, its
input impedance ZPA changes considerably, thus altering the
capacitance seen at the input of the buffer (load pulling). Also,
upon turning on, the PA draws a very high current from the
system supply, reducing its voltage by tens or perhaps hundreds
of millivolts and changing the VCO frequency

To alleviate the foregoing issues, the VCO can remain


locked while sensing the baseband data. That is, the PLL
continuously monitors and corrects the VCO output.
Advantages compared to quadrature modulator
First, in contrast to a quadrature GMSK modulator, it
requires much less processing of the baseband data.
Second, it obviates the need for the quadrature phases
of the LO. Of course, this method can be applied only to
constant-envelope modulation schemes

Divider Design
integer-N synthesizers produce an output frequency that
is an integer multiple of the reference frequency
If N increases by 1, then fout increases by fREF; i.e., the
minimum channel spacing is equal to the reference
frequency
The divide ratio must be programmable from, say, N1 to
N2 so that N1fREF = f1 and N2fREF = f2

fREF: it must be equal to the desired channel spacing


and it must be the greatest common divisor of f1 and f2.

Design challenges in divider design


(1) the divider modulus, N, must change in unity steps,
(2) the first stage of the divider must operate as fast as
the VCO,
(3) the divider input capacitance and required input
swing must be commensurate with the VCO drive
capability,
(4) the divider must consume low power, preferably
less than the VCO.

Pulse Swallow Divider


common realization of the feedback divider that allows unity steps in the
modulus is called the pulse swallow divider.Has 3 parts
dual-modulus prescaler; this counter provides a divide ratio of N + 1 or N
according to the logical state of its modulus control input.
A swallow counter; this circuit divides its input frequency by a factor of
S, which can be set to a value of 1 or higher in unity steps by means of the
digital input.This counter controls the modulus of the prescaler and also
has a reset input. The swallow counter is typically designed as an
asynchronous circuit for the sake of simplicity and power savings.
A program counter; this divider has a constant modulus, P. When the
program counter fills up (after it counts P pulses at its input), it resets
the swallow counter.
Overall division modulus-(N+1).S+N(P-S)=NP+S

Choice of Prescaler Modulus


to cover the Bluetooth channels from 2400 MHz to 2480
MHz, we can choose N = 4, P = 575, and S = 100, ..., 180,
or N = 10, P = 235, and S = 50, ..., 130.
requiring a large N so as to permit a long delay through
the asynchronous stages and the feedback loop.
a larger prescaler modulus leads to a higher
power dissipation if the stages within the prescaler
incorporate current steering to operate at high speeds
For this reason, the prescaler modulus is determined by
careful simulations.
Divided by2/3

Divider Logic Styles


The divider blocks in the feedback loop of a synthesizer can
be realized by means of various logic styles.
The choice of a divider topology is governed by several
factors:
the input swing (e.g., that available from the VCO), the
input capacitance (e.g., that presented to the VCO),
the maximum speed,
the output swing (as required by the subsequent stage),
the minimum speed (i.e.,dynamic logic versus static logic),
and the power dissipation.

The MOS current mode logic (MCML) circuit,which is of


high power consumption, is commonly used to achieve
the high operating frequency,
while a true singlephase clock (TSPC) dynamic circuit,
which only consumes power during switching, has a
lower operating frequency
[13].
To get high operating frequency Extended True Single
Phase Clock (E-TSPC) is used.

Current-Steering Circuits- currentmode logic (CML),


current-steering logic, also known as current-mode logic (CML),
operates with moderate input and output swings.
CML circuits provide differential outputs and hence a natural
inversion; e.g., a single stage serves as both a NAND gate and an
AND gate.
CML derives its speed from the property that a differential pair can
be rapidly enabled and disabled through its tail current source.
The circuit is typically designed for a single-ended output swing of
RDISS = 300 mV, and the
transistors are sized such that they experience complete switching
with such input swings.

Divide by 2 ckt consisting two


cml latch in feedback
The stacking of the differential
and regenerative pairs atop the
clocked pair does not lend itself
to low supply voltages.
This issue is alleviated by
omitting the tail current source,
but the bias currents of the circuit
must still be defined accurately.
the bias of the clocked pair is
defined by a current mirror and
the clock is coupled capacitively.

The value of the coupling


capacitors is chosen about 5 to 10
times the gate capacitance of M5
and M6 to minimize the attenuation
of the clock amplitude.
Resistors RB1 and RB2 together
with C1 and C2 yield a time
constant much longer than the
clock period.
capacitive coupling may be
necessary even with a tail current if
the VCO output CM level is
incompatible with the latch input
CM level

large clock swings allow transistors M5 and M6 to operate in


the class AB mode, i.e., their peak currents well exceed their
bias current. This attribute improves the speed of the divider

For the 2 stage to run at


high frequencies, the
speed of the D latch must
be maximized.
For example, inductive
peaking raises the
bandwidth at the output
nodes

True Single-Phase Clocking