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MODERN FPGA

Presented by
NIELIT,Chennai

1

Major FPGA Vendors

SRAM-based FPGAs
• Xilinx, Inc.
~ 51% of the market
~ 85%
• Altera Corp. ~ 34% of the market
• Lattice Semiconductor
• Atmel
• Achronix
• Tabula
Flash & antifuse FPGAs
• Actel Corp. (Microsemi SoC Products Group)
• Quick Logic Corp.

Xilinx FPGA Families

High-performance families
– Virtex (220 nm)
– Virtex-E, Virtex-EM (180 nm)
– Virtex-II (130 nm)
– Virtex-II PRO (130 nm)
– Virtex-4 (90 nm)
– Virtex-5 (65 nm)
– Virtex-6 (40 nm)
– Virtex-7 (28 nm)
Low Cost Family
– Spartan/XL – derived from XC4000
– Spartan-II – derived from Virtex
– Spartan-IIE – derived from Virtex-E
– Spartan-3 (90 nm)
– Spartan-3E (90 nm) – logic optimized
– Spartan-3A (90 nm) – I/O optimized
– Spartan-3AN (90 nm) – non-volatile,
– Spartan-3A DSP (90 nm) – DSP optimized
– Spartan-6 (45 nm)
– Artix-7 (28 nm)

Xilinx FPGA Devices Technology Low-cost 120/150 nm 90 65 45 40 nm nm nm nm Spartan 3 Highperformanc e Virtex 2. 2 Pro Virtex 4 Virtex 5 Spartan 6 Virtex 6 .

LUTs & ALUTs ECE 448 – FPGA and ASIC Design with VHDL .

4-bit LUTs vs. 6-bit LUTs 6-bit LUTs introduced in Virtex 5 .

Major Differences between Xilinx Families

Look-Up Tables

Spartan 3
Virtex 4

Virtex 5, Virtex 6,
Spartan 6

4-input

6-input

Number of CLB slices
per CLB

4

2

Number of LUTs
per CLB slice

2

4

Major Differences between Xilinx Families
Spartan 3
Virtex 4
Maximum Single-Port
Memory Size per LUT

16 x 1

Maximum Shift Register
Size per LUT

16 bits

Number of adder
stages per CLB slice

2

Virtex 5, Virtex 6,
Spartan 6
64 x 1
32 bits
4

ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. and Flows. Tools.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL 10 .Multipliers in Spartan 3 The Design Warrior’s Guide to FPGAs Devices. (www.

DSP Units ECE 448 – FPGA and ASIC Design with VHDL .

and Virtex 6 12 .Xilinx XtremeDSP • Starting with Virtex 4 family. Xilinx introduced DSP48 block for high-speed DSP on FPGAs • Essentially a multiply-accumulate core with many other features • Now also in Spartan-3A. Spartan 6. Virtex 5.

Multiplier-Accumulator .MAC 13 .

Mathematical Functions • DSP 48 can perform mathematical functions such as: • • • • • • • • • Add/Subtract Accumulate Multiply Multiply-Accumulate Multiplexer Barrel Shifter Counter Divide (multi-cycle) Square Root (multi-cycle) • Can also create filters such as: • • • • Serial FIR Filter (Xilinx calls this MACC filters) Parallel FIR Filter Semi-Parallel FIR Filter Multi-rate FIR Filters 14 .

DSP48 Slice: Virtex 4 15 .

Simplified Form of DSP48 Adder Out = (Z ± (X + Y + CIN)) 16 .

Choosing Inputs to DSP Adder P = Adder Out = (Z ± (X + Y + CIN)) 17 .

DSP48E Slice : Virtex5 18 .

New in Virtex 5 Compared to Virtex 4 19 .

Xilinx DSP48 20 .

Stratix III DSP Unit .

Embedded Memories ECE 448 – FPGA and ASIC Design with VHDL .

Memory Types Memory RAM ROM Memory Single port Dual port Memory With asynchronous read With synchronous read 23 .

Memory Types in Xilinx Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Memory Inferred Instantiated Manually Using Core Generator 24 .

20K) (144K.Memory Types in Altera Memory Distributed (ALUT-based. 512K) Memory Inferred Instantiated Manually Using MegaWizard Plug-In Manager 25 . 9K. Stratix III onwards) Memory block-based Small size (512) Medium size Large size (4K.

Memory Modes The M4K memory blocks support the following modes:  Single-port RAM (RAM:1-Port)      Simple dual-port RAM (RAM: 2-Port) True dual-port RAM (RAM:2-Port) Tri-port RAM (RAM:3-Port) Single-port ROM (ROM:1-Port) Dual-port ROM (ROM:2-Port) .

mif file is used to initialize the ROM contents .Single-Port ROM • The address lines of the ROM are registered • The outputs can be registered or unregistered • A .

Stratix II TriMatrix Memory .

Stratix II TriMatrix Memory .

Stratix III & Stratix IV TriMatrix Memory .

Stratix II & III Shift-Register Memory Configuration .

Supply Voltage ECE 448 – FPGA and ASIC Design with VHDL .

0 0.5 1.9 0.3 2.9 ECE 448 – FPGA and ASIC Design with VHDL .8 1.5 1.Change in Supply Voltages Year 1998 1999 2000 2001 2003 2008 2009 2011 Technology (nm) 350 250 180 150 130 65 40 28 Core Supply Voltage (V) 3.2 1.

Gigabit Transceivers ECE 448 – FPGA and ASIC Design with VHDL .

Using a Bus to Communicate Between Devices The Design Warrior’s Guide to FPGAs Devices. Tools.com) . and Flows. (www. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp.mentor.

and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp.Using High-Speed Tranceivers to Communicate Between Devices The Design Warrior’s Guide to FPGAs Devices.com) ECE 448 – FPGA and ASIC Design with VHDL . (www. Tools.mentor.

Using High-Speed Tranceivers to Communicate Between Devices The Design Warrior’s Guide to FPGAs Devices. (www.mentor.com) . and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. Tools.

mentor.com) . and Flows.Effect of Noise on Single Wire and Differential Pair The Design Warrior’s Guide to FPGAs Devices. (www. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. Tools.

com) . ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp.mentor. and Flows. (www.Generating a Differential Pair The Design Warrior’s Guide to FPGAs Devices. Tools.

(www.mentor.Multiple Standards for High-Speed Serial Communication Fibre Channel InfiniBand PCI Express (developed by Intel) RapidIO SkyRail (developed by MindSpeed Technologies) 10-gigabit Ethernet The Design Warrior’s Guide to FPGAs Devices. Tools. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. and Flows.com) .

com) . Tools. and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.Using FPGA to Interface Between Multiple Standards The Design Warrior’s Guide to FPGAs Devices.mentor.

mentor.com) .Ganging Multiple Transceivers Together The Design Warrior’s Guide to FPGAs Devices. and Flows. Tools. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.

com) . ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. and Flows.An Ideal Signal vs.mentor. (www. Signal Seen by Receiver The Design Warrior’s Guide to FPGAs Devices. Tools.

and Flows. (www.The Effects of Transmitting a Series of Identical Bits The Design Warrior’s Guide to FPGAs Devices. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. Tools.mentor.com) .

Tools.com) . (www.mentor.Main Elements of the Transceiver Block The Design Warrior’s Guide to FPGAs Devices. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. and Flows.

Recovering Clock Signal .

Sampling the Incoming Signal .

Xilinx ML605 Evaluation Kit $1795 .

PLDA XpressV6 Design Kit $3990 .

HiTech Global PCI Express Gen 2 / SFP+ / USB 3.0 Development Board $2995 .

HiTech Global HXT 8-lane PCI Express/4port SFP+ Optical Network Card $8995 .

HiTech Global HXT 16-lane PCI Express Optical Network Card $8995 .

PLDA XpressGX4LP Design Kit $4990 .

HiTech Global GT/GX PCI Express Gen 2 / 3 & Optical Development Platform/Networking Card $5995 .

Terasic DE4 Development and Education Board $2995 .

Gutz Logic PCI Express x1 Demo Board (Actel FPGA) .

LatticeSC PCI Express x4 Evaluation .

0 x8 8 GB/s $5995 Terasic DE4 Board GX530 (max) 8GB (max) General Purpose 2.0 x8 4 GB/s $4495 PLDA XpressGX4LP GX530 (max) 2GB (max) High Speed Eth. 2.1 x1 250 MB/s N/A 32MB PCIe Evaluation 1.0 LX550T (max) 8GB (max) General Purpose 2.0 x8 4 GB/s $2995 A3P1000 1MB PCIe Evaluation 1. 2.0 x16 8 GB/s $8995 Boards based on Altera Stratix IV Altera Stratix IV GX Kit GX530 (max) 512MB General Purpose 2.1 x8 / 2.0 x4 2 GB/s $1795 PLDA XpressV6 Design Kit LX550T (max) 8GB (max) General Purpose 2.0 x8 4 GB/s $3990 HiTech Global PCI Express / USB 3. 3. 2.0 x8 4 GB/s $4990 HiTech Global GT/GX PCIe & Optical 100G5 (max) 4GB (max) High Speed Eth.0 x8 4 GB/s $8995 HiTech Global HXT 16-lane Optical HX565T (max) 16GB (max) High Speed Eth.Board Overview Manufacturer Name FPGA Memory Application PCIe Throughput Base Price Boards based on Xilinx Virtex-6 Xilinx ML605 Evaluation Kit LX240T-1 2GB (max) General Purpose 1.0 x8 4 GB/s $2995 HiTech Global HXT 8-lane Optical HX565T (max) 16GB (max) High Speed Eth.1 x4 1 GB/s N/A Boards based on Actel ProASIC3 Gutz Logic PCI e x1 Demo Board Boards based on Lattice Semiconductor LatticeSC Lattice LatticeSC PCIe x4 Board ECP2M-50 .

Embedded Microprocessors ECE 448 – FPGA and ASIC Design with VHDL .

(www.com) ECE 448 – FPGA and ASIC Design with VHDL . and Flows. Tools. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp.mentor.Embedded Microprocessor Cores The Design Warrior’s Guide to FPGAs Devices.

Virtex-II Pro Architecture 2 3 Features: 1. 5. 2. 4. Processor Block RocketIO Multi-Gigabit Transceivers CLB and Configurable Logic SelectIO-Ultra Digital Clock Managers Multipliers and Block SelectRAM 1 6 4 ECE 448 – FPGA and ASIC Design with VHDL 5 . 3. 6.

ECE 448 – FPGA and ASIC Design with VHDL .

PowerPC Cores PowerPC System PowerPC System ECE 448 – FPGA and ASIC Design with VHDL .

Embedded Development Kit (EDK) Software Flow Hardware Flow Processor IP. Microprocessor Peripheral Description Files VHDL / Verilog C / C++ Code Libraries PlatGen Synthesizer Compiler LibGen Microprocessor Hardware Specification File EDIF IP Netlists Object Files Microprocessor Software Specification File ISE / Xflow Linker System Constraint File Bitstream Data2MEM Executable Download to FPGA ECE 448 – FPGA and ASIC Design with VHDL .

Zynq .Extensible Processing Platform ECE 448 – FPGA and ASIC Design with VHDL .

Zynq – 7000 EPP ECE 448 – FPGA and ASIC Design with VHDL .

Zynq – 7000 Product Table ECE 448 – FPGA and ASIC Design with VHDL .