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You are on page 1of 51

**COLLAGE OF ENGINEERING & TECHNOLOGY
**

Department of Electrical and Computer

Engineering

Logic and

Computer Design

Course name:

Electrical

Fundamentals

Chapter

1 – Digital

measurement

& instrumentation

Course

code: ECEg4155

Computers

and Information

Course instructor: Getnet Z.

Contact information:

Kime & Thomas Kaminski

Email: Charles

abaye.get@gmail.com

© 2004 Pearson

Education, Inc.

Consultation

hours:

Terms of Use

Wednesday:

(Hyperlinks from

are active3:00-5:00

in View Show mode)

OUT LINE

Introduction to ADC

Conversion Process

Examples of ADC applications

Types of ADC

DAC

1/2/17

ECEg:4155

2

INTRODUCTION TO ADC

SIGNAL TYPES

1/2/17

ECEg:4155

Analog Signals

Any continuous signal that

a time varying variable of

the signal is a

representation of some

other time varying quantity

Measures

one quantity in

terms of some other quantity

Examples

**Speedometer needle as function
**

of speed

Radio volume as function of

knob movement

t

3

SIGNAL TYPES

Binary

**Computers can only
**

perform processing on

digitized signals

1

ECEg:4155

States

On and of

1/2/17

Digital Signals

Consist of only two states

0

4

**ANALOG-DIGITAL CONVERTER
**

(ADC)

An electronic integrated circuit which converts a

signal from analog (continuous) to digital

(discrete) form

Provides a link between the analog world of

transducers and the digital world of signal

processing and data handling

1/2/17

ECEg:4155

5

**ANALOG-DIGITAL CONVERTER
**

(ADC)

An electronic integrated circuit which converts a

signal from analog (continuous) to digital

(discrete) form

Provides a link between the analog world of

transducers and the digital world of signal

processing and data handling

1/2/17

ECEg:4155

6

t

**ANALOG-DIGITAL CONVERTER
**

(ADC)

An electronic integrated circuit which converts a

signal from analog (continuous) to digital

(discrete) form

Provides a link between the analog world of

transducers and the digital world of signal

processing and data handling

1/2/17

ECEg:4155

7

t

**ADC CONVERSION PROCESS
**

1/2/17

**Two main steps of process
**

1.

Sampling and Holding

2.

Quantization and Encoding

ECEg:4155

**Analog-to-Digital Converter
**

Quantizing

and

Encoding

Sampling and

Hold

Input: Analog

Signal

t

t

8

ADC PROCESS

Sampling & Hold

Ideally

**twice as fast as what
**

we are sampling

Continuous Signal

**Digital system works with
**

discrete states

Taking

**samples from each
**

location

ECEg:4155

**Measuring analog signals at
**

uniform time intervals

1/2/17

**Reflects sampled and hold
**

signal

Digital

approximation

t

9

ADC PROCESS

Sampling & Hold

1/2/17

ECEg:4155

**Measuring analog signals at
**

uniform time intervals

Ideally

**twice as fast as what
**

we are sampling

**Digital system works with
**

discrete states

Taking

**samples from each
**

location

**Reflects sampled and hold
**

signal

Digital

approximation

t

10

ADC PROCESS

Sampling & Hold

1/2/17

ECEg:4155

**Measuring analog signals at
**

uniform time intervals

Ideally

**twice as fast as what
**

we are sampling

**Digital system works with
**

discrete states

Taking

**a sample from each
**

location

**Reflects sampled and hold
**

signal

Digital

approximation

t

11

ADC PROCESS

Sampling & Hold

1/2/17

ECEg:4155

**Measuring analog signals at
**

uniform time intervals

Ideally

**twice as fast as what
**

we are sampling

**Digital system works with
**

discrete states

Taking

**samples from each
**

location

**Reflects sampled and hold
**

signal

Digital

approximation

t

12

ADC PROCESS

Encoding

ECEg:4155

1/2/17

Quantizing

Separating the input

signal into a discrete

states with K increments

K=2N

**Assigning a unique digital code to each state for
**

input into the microprocessor

**N is the number of bits of
**

the ADC

**Analog quantization size
**

Q=(Vmax-Vmin)/2N

Q

**is the Resolution
**

13

ADC PROCESS

Quantization & Coding

ECEg:4155

Use original analog signal

1/2/17

14

ADC PROCESS

Quantization & Coding

1/2/17

**Use original analog signal
**

Apply 2 bit coding

1

1

1

0

0

1

0

0

ECEg:4155

K=22

00

01

10

11

15

ADC PROCESS

Quantization & Coding

1/2/17

**Use original analog signal
**

Apply 2 bit coding

1

1

1

0

0

1

0

0

ECEg:4155

K=22

00

01

10

11

16

ADC PROCESS

Quantization & Coding

1/2/17

**Use original analog signal
**

Apply 3 bit coding

ECEg:4155

K=23

000

001

010

011

100

101

110

111

17

ADC PROCESS

Quantization & Coding

1/2/17

**Use original analog signal
**

Apply 3 bit coding

Better representation of

input information with

additional bits

MCS12 has max of 10 bits

ECEg:4155

K=23

000

001

010

011

100

101

110

111

K=16

0000

.

.

.

1111

K=…

18

**ADC PROCESS-ACCURACY
**

The accuracy of an ADC can be improved by increasing:

1/2/17

ECEg:4155

t

Sampling Rate, Ts

Based on number of steps

required in the conversion

process

Increases the maximum

frequency that can be

measured

t

Resolution, Q

**Improves accuracy in measuring amplitude of
**

analog signal

Limited by the signal-to-noise ratio (~6dB)

19

ADC PROCESS-ACCURACY

**The accuracy of an ADC can be improved by increasing:
**

1/2/17

ECEg:4155

Sampling Rate, Ts

Based on number of steps

required in the conversion

process

Increases the maximum

frequency that can be

measured

t

t

**Resolution (bit depth), Q
**

**Improves accuracy in measuring amplitude of
**

analog signal

20

**ADC-ERROR POSSIBILITIES
**

Aliasing (sampling)

**when the input signal is changing much faster
**

than the sample rate

Should follow the Nyquist Rule when sampling

Answers question of what sample rate is required

Use a sampling frequency at least twice as high as the

maximum frequency in the signal to avoid aliasing

f

sample>2*fsignal

ECEg:4155

Occurs

1/2/17

**Quantization Error (resolution)
**

Optimize

resolution

Dependent on ADC converter of microcontoller

21

ADC APPLICATIONS

Microphones

Strain

Gages

Thermocouple

Digital Multimeters

ECEg:4155

**ADC are used virtually everywhere where an
**

analog signal has to be processed, stored, or

transported in digital form

1/2/17

22

TYPES OF ADC

1/2/17

ECEg:4155

**Successive Approximation A/D Converter
**

Flash A/D Converter

Dual Slope A/D Converter

Delta-Sigma A/D Converter

23

**SUCCESSIVE APPROXIMATION ADC
**

•

•

•

•

**DAC = Digital to Analog Converter
**

EOC = End of Conversion

SAR = Successive Approximation Register

S/H = Sample and Hold Circuit

Vin = Input Voltage

•

Comparator

•

Vref = Reference Voltage

ECEg:4155

•

Elements

1/2/17

24

**SUCCESSIVE APPROXIMATION ADC
**

•

Uses an n-bit DAC and original analog results

•

Performs a binary comparison of VDAC and Vin

•

MSB is initialized at 1 for DAC

•

If Vin < VDAC (VREF / 2^n=1) then MSB is reset to 0

•

If Vin > VDAC (VREF / 2^n) Successive Bits set to 1 otherwise 0

•

Algorithm is repeated up to LSB

•

At end DAC in = ADC out

•

N-bit conversion requires N comparison cycles

ECEg:4155

Algorithm

1/2/17

25

**5-bit ADC, Vin=0.6V, Vref=1V
**

Cycle 1 => MSB=1

Vin < VDAC

Voltage .5 .25 .125

SAR unchanged = 1 0 0 0 0

1

0

.0625 .03125

SAR bit3 reset to 0 = 1 0 0 0 0

SAR bit2 reset to 0 = 1 0 0 0 0

Cycle 4

SAR = 1 0 0 1 0

VDAC = .5+.0625=.5625 Vin > VDAC

2

Cycle 3

SAR = 1 0 1 0 0

VDAC = .5 + .125 = .625

3

Cycle 2

SAR = 1 1 0 0 0

VDAC = .5 +.25 = .75 Vin < VDAC

4

ECEg:4155

SAR = 1 0 0 0 0

VDAC = Vref/2^1 = .5 Vin > VDAC

Bit

1/2/17

**SUCCESSIVE APPROXIMATION ADC EXAMPLE
**

DAC bit/voltage

Cycle 5

SAR unchanged = 1 0 0 1 0

SAR = 1 0 0 1 1

VDAC = .5+.0625+.03125= .59375

Vin > VDAC

SAR unchanged = 1 0 0 1 1

26

**SUCCESSIVE APPROXIMATION ADC
**

reliable

successive approximation

Medium accuracy compared to

ADC’s will be slower

**other ADC types
**

Good tradeoff between speed and

Higher resolution

ECEg:4155

Capable of high speed and

Disadvantages

1/2/17

Advantages

Speed limited to ~5Msps

cost

**Capable of outputting the binary
**

number in serial (one bit at a

time) format.

27

FLASH ADC

**Encoder – Converts output of
**

comparators to binary

• Comparators

•

ECEg:4155

**Also known as parallel ADC
**

Elements

1/2/17

28

FLASH ADC

Algorithm

Resolution ;

N= Encoder Output bits

Comparators => 2N-1

**Example: Vref8V, Encoder 3-bit
**

ECEg:4155

Vin value lies between two comparators

1/2/17

Resolution = 1.0V

Comparators 23-1=7

**1 additional encoder bit -> 2 x #
**

Comparators

29

**FLASH ADC EXAMPLE
**

0

0

Vcomp5 = Vref*5/8 = 5V

1

1

Vcomp6 = Vref*6/8 = 6V

ECEg:4155

Vin lies in between Vcomp5 & Vcomp6

1/2/17

Vin = 5.5V, Vref= 8V

1

Comparator 1 - 5 => output 1

Comparator 6 - 7 => output 0

1

5.5V

Encoder Octal Input = sum(0011111) = 5

1

**Encoder Binary Output = 1 0 1
**

30

FLASH ADC

efficient in terms

of speed, very fast

**limited only in terms of
**

comparator and gate

propagation delays

Lower

ECEg:4155

Most

Disadvantages

1/2/17

Advantages

Simplest in terms of

operational theory

resolution

Expensive

For each additional

output bit, the number

of comparators is

doubled

**i.e. for 8 bits, 256
**

comparators needed

31

**DUAL SLOPE A/D CONVERTER
**

**Also known as an Integrating ADC
**

1/2/17

ECEg:4155

+

_

Clock

Start

Control

Logic

Counter

Stop

32

**DUAL-SLOPE ADC – HOW IT WORKS
**

**The input voltage is computed as a function of the reference
**

voltage, the constant run-up time period, and the measured rundown time period

The run-down time measurement is usually made in units of the

converter's clock, so longer integration times allow for

higher resolutions

ECEg:4155

**Then, a known reference voltage of opposite polarity is applied to
**

the integrator and is allowed to ramp until the integrator output

returns to zero (td)

1/2/17

**An unknown input voltage is applied to the input of the integrator
**

and allowed to ramp for a fixed time period (tu)

**The speed of the converter can be improved by sacrificing
**

resolution

td

Vin Vref

tu

33

DUAL SLOPE A/D CONVERTER

ECEg:4155

Disadvantages

Slow

High precision

external components

required to achieve

accuracy

1/2/17

Advantages

Input signal is

averaged

Greater noise

immunity than other

ADC types

High accuracy

34

**DELTA-SIGMA A/D CONVERTER
**

Low-Pass

Filter

Digital

Outpu

t

ECEg:4155

Delta-Sigma

Modulator

1/2/17

Analog

Input

35

**DELTA-SIGMA ADC – HOW IT WORKS
**

Input over sampled, goes to integrator

Integration compared with ground

Iteration drives integration of error to zero

Output is a stream of serial bits

1/2/17

ECEg:4155

36

DELTA-SIGMA A/D CONVERTER

resolution

Slow

due to

oversampling

ECEg:4155

High

Disadvantages

1/2/17

Advantages

No

precision external

components needed

37

COMPARISON OF ADC’S

Dual Slope

Slow

Med

12-16

Flash

Very Fast

High

4-12

Successive

Approx

Medium –

Fast

Low

8-16

Sigma –

Delta

Slow

Low

12-24

(bits)

ECEg:4155

(relative)

Resolution

1/2/17

(relative)

Cost

Type

Speed

38

DIGITAL-TOANALOG

CONVERSION

[DAC]

DIGITAL-TO-ANALOG

CONVERSION

1/2/17

ECEg:4155

**Digital to Analog conversion involves
**

transforming the computer’s binary output in 0’s

and 1’s (1’s typically = 5.0 volts) into an analog

representation of the binary data

When data is in binary form, the 0's and 1's may

be of several forms such as the TTL form where

the logic zero may be a value up to 0.8 volts and

the 1 may be a voltage from 2 to 5 volts.

The data can be converted to clean digital form

using gates which are designed to be on or of

depending on the value of the incoming signal.

40

DIGITAL-TO-ANALOG

CONVERSION

1/2/17

ECEg:4155

**Data in clean binary digital form can be
**

converted to an analog form by using a summing

amplifier.

For example, a simple 4-bit D/A converter can be

made with a four-input summing amplifier.

41

DIGITAL-TO-ANALOG

CONVERSION

Basic Approaches

Summing Amplifier

R-2R Network Approach

ECEg:4155

Weighted

1/2/17

2

42

**WEIGHTED SUM DAC
**

One way to achieve D/A conversion is to use a

summing amplifier.

Consider the following 8-bit DAC

1/2/17

ECEg:4155

43

**WEIGHTED SUM DAC
**

**E.g: consider the following 4-bit WSDAC
**

1/2/17

ECEg:4155

44

**WEIGHTED SUM DAC
**

1/2/17

ECEg:4155

**This approach is not satisfactory for a large
**

number of bits because it requires too much

precision in the summing resistors.

This problem is overcome in the R-2R network

DAC.

45

R-2R LADDER DAC

1/2/17

ECEg:4155

46

R-2R LADDER DAC

1/2/17

ECEg:4155

47

R-2R LADDER DAC

ECEg:4155

**summing amplifier with the R-2R ladder
**

of resistances shown produces the output

where the D's take the value 0 or 1.

The digital inputs could be TTL voltages

which close the switches on a logical 1 and

leave it grounded for a logical 0.

This is illustrated for 4 bits, but can be

extended to any number with just the

resistance values R and 2R.

1/2/17

The

48

1/2/17

ECEg:4155

u

o

y

k

n

a

h

T

49

1/2/17

ECEg:4155

50

Q?

QUIZ

1/2/17

ECEg:4155

**1 write what you understand from today's class.
**

2 diferentiate between ADC and DAC by giving

example for the respective converters.

51

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