CMOS Fabrication

EMT 251
 Objectives
To discussed the fundamentals of
CMOS fabrication steps.
To examined the major steps of the
process flow.
To overview the cross section view of
a circuit
Chip making Process
 Introduction
MOSFET

NMOS PMOS CMOS

 MOSFET

Gate

Drain Source

Metal Oxide Semiconductor Field Effect Transistor

Source (Arsenic, Phosphorous, Boron)

Drain (Arsenic, Phosphorous, Boron)

Gate (Aluminum, Polysilicon)

 NMOS

P-type substrate

N-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 NMOS

P-type substrate

N-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 PMOS

N-type substrate

P-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 PMOS

N-type substrate

P-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 CMOS

A combination of both NMOS & PMOS technology

Most basic example: inverter

PROCESS FLOW
WELL FORMATION

ISOLATION FORMATION

TRANSISTOR MAKING

INTERCONNECTION

PASSIVATION
CMOS FABRICATION PROCESS
well formation

Start with clean p-type

substrate (p-type wafer)
CMOS FABRICATION PROCESS
well formation

Grow epitaxy layer (made from

SiO2) as mask layer for well
formation
CMOS FABRICATION PROCESS
well formation

Well will be formed

here

By *photolithography and etching

process, well opening are made
*photolithography and etch processes are shown in next slides
 Photolithography (CED)
photoresist

Si02
P-substrate Photoresist coating (C)

UV light

mask Masking and exposure

Opaque
under UV light(E)
area Resist dissolved after
P-substrate
Transparent developed (D)
area
Pre-shape the well
pattern at resist layer
 etching

Removing the unwanted

P-substrate pattern by wet etching

Resist clean
P-substrate
Desired pattern formed
CMOS FABRICATION PROCESS
well formation

Phosphorus ion

Ion bombardment by ion implantation

SiO2 as mask, uncovered area will
exposed to dophant ion
CMOS FABRICATION PROCESS
isolation formation

Thick oxide

Increase SiO2 thickness by

oxidation at high temperature
Oxide will electrically isolates
nmos and pmos devices
CMOS FABRICATION PROCESS
transistor making

nmos will pmos will

be formed be formed
here here

LOCOS (isolation structure)

By photolithography and etching

process, pmos and nmos areas
are defined
CMOS FABRICATION PROCESS
transistor making

Gate oxide

Grow very thin gate oxide at

elevated temperature in very
short time
CMOS FABRICATION PROCESS
transistor making

polisilicon

Deposit polisilicon layer

CMOS FABRICATION PROCESS
transistor making

gate

Photolithography (photo) and

etching to form gate pattern
 CMOS FABRICATION PROCESS
transistor making
Arsenic ion

photoresist

Photo process to define the nmoss

active (source and drain) area and
VDD contact
Ion implantation with Arsenic ion for
n+ dophant.
Photoresist and polisilicon gate act as
mask
CMOS FABRICATION PROCESS
transistor making

VDD
source drain contact

Nmoss Source and drain with VDD

contact formation
Resist removal
CMOS FABRICATION PROCESS
transistor making

Boron ion

photoresist

Photo process to define the GND contact

and pmoss active area (source and drain)
Ion implantation with boron ionto have p+
dophant
Photoresist and gate act as mask
CMOS FABRICATION PROCESS
transistor making

GND
contact Pmoss Pmos
drain source

Pmoss source and drain

formation with GND contact
Resist removal
CMOS FABRICATION PROCESS
interconnection

SiO2

Deposit SiO2 layer through

out wafer surface
CMOS FABRICATION PROCESS
interconnection

contact

Photo and etching process to

make contact
CMOS FABRICATION PROCESS
interconnection

Metal 1

Metal 1 deposition throughout

wafer surface
CMOS FABRICATION PROCESS
interconnection

Photo and etching processes to

pattern interconnection
Mask Layout
Mask Layout
Mask Layout
Mask Layout
 A
A

Metal 1
oxide
n+ n+ p+ p+ n+
N-well

p-substrate
Assignment
B

B
 GLOSSARY
Photolithography (photo)
Process of transferring pattern on mask to photoresist layer on wafer
surface (pre-pattern the chip)
Etching
Process of permanently removed the unwanted part of design on wafer
surface to get the desired pattern
Diffusion
Process of introducing dophant layer by movement of dophant atoms
from high concentration to low concentration area at high temperature
Ion implantation
Process of introducing dophant layer by bombardment of high energy
dophant ion in high electric field chamber
Oxidation
Process of growing thick or thin SiO2 layer depend on oxide application
CMP
Process to physically grind flat to have a planar surface for better
exposure at photo process.
THE END