Modelling of SOI-LDMOS Transistor

D.Sai.Chaitanya
14311D6823
VLSI and Embedded Systems

• MM20 model includes the channel region and the drift region which is the basic structure of LDMOS region 1 and region 2. • This model describes the characteristics of the MOSFET where the drain and source of the device are at longer distance than the conventional MOSFET. .• The LDMOS model is build on the basis of MM20 MOSFET model. • Next step in this model is to extend this structure by including the drift region through which the high voltage performance characteristics are obtained.

• Thus the three regions are now model and the LDMOS basic model is obtained.• Now in order to include the high voltage operation region that is the drift region which is under no gate control is modeled by using the MM40 MOSFET model which includes the required region. .

these are shown in the below figure. .• Basic High voltage MOSFET strategy is shown below • The LDMOS model thus can be modeled as a mosfet in conjunction with the resistor which is to model the drift region and the diode part which is formed between base and channel region.

8um and it is Silicon on insulator LDMOS with insulator as silicon dioxide .• The design that was modelled to study the characteristics of LDMOS is shown below • The LDMOS has a channel length of 1.

.8um and 2.2 um.• The V-I characteristics of the shown ldmos are obtained and by changing parameters like the channel length . oxide and gate length. • The two channel lengths are 1. • The two oxides used are halfnioum oxide and silicon dioxide. • The graphs of Vds vs Id and Vgs vs Id for two oxides and two different channel lengths are obtained.

SiO2 and HfO2. .8um and two different oxide materials i.• Results • The below graph show the Vds vs Id graph with channel length of 1. Vgs voltages are 5v and 10v.e.

e. Vgs voltages are 5v and 10v. .2 um and two different oxide materials i.• The below graph show the Vds vs Id graph with channel length of 2. SiO2 and HfO2.

8 um and two different oxide materials i. Vds voltages are 5v and 10v. SiO2 and HfO2.• The below graph show the Vgs vs Id graph with channel length of 1. .e.

SiO2 and HfO2.• The below graph show the Vgs vs Id graph with channel length of 2.2um and two different oxide materials i. .e. Vds voltages are 5v and 10v.

• The circuit level model of the LDMOS is shown below Thus the LDMOS is modelled by considering the charge equations and including the quasi-saturation effect .

999–1007. Oct. K. no. Chakravorty.. Nov. Tanaka et al. M. pp. “A surfacepotential-based high-voltage compact LDMOS transistor model. 2072–2080. M.” in POWER/HVMOS Devices Compact Modeling. N. No. No. Oritsuki et al. 52. Amsterdam. van Langevelde. . no. vol. Vol. Workshop Electron Devices Semiconductor. Aarts and A. Radhakrishna. 58. 2010. vol. A. no.” An Improved Quasi- Saturation and Charge Model for SOI-LDMOS Transistors. A. Mittal. Jun.. Electron Devices.•REFERENCE • Title: “Modelling of LDMOS Transistor” • Name: D.Chaitanya • Roll. DasGupta. Tajic. “Compact modeling of SOI-LDMOS including quasisaturation effect. May 2005. 2010. C. Chakravorty. 2011. 2006. 3. “Modeling of SOI-LDMOS transistor including impact ionization. and R. A. Electron Devices. 57. “HiSIM-HV: A compact model for simulation of high-voltage MOSFET circuits. vol.” IEEE Trans.Amitava DasGupta and Anjan Chakravorty. • [5] T. 2009. and A.” IEEE Trans. Electron Devices. 62. • [2] P. • [8] A. pp. 58. N. Holland and P. Microelectron. (IEDST). • [3] A. vol. “MM20 HVMOS model: A surface-potential-based LDMOS model for circuit simulation. “Quasi-2-dimensional compact resistor model for the drift region in high-voltage LDMOS devices. 11.. 5. DasGupta.: 14311D6823 • Specialization: VLSI & Embedded System • [1] Nitin Prasad. and N. Electron Devices.” IEEE Trans.” in Proc. • [6] U.S. DasGupta. Lekshmi. and self-heating. “An alternative process architecture for CMOS based high side RESURF LDMOS transistors. Jul. • [7] Y. 2nd Int. March 2015. 7. 2011. Igic. A. Aarts.” in International Conf. Technol. • [4] A. DasGupta. T.” IEEE Trans. The Netherlands: Springer-Verlag. D’Halleweyn. snapback. Prasad Sarangapani .” IEEE Transactions on Electon Devices.