201 - ASP v8.0

201ASP
Mid-Range Family Peripheral

Configuration and Assembly
Programming
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 JanuarySlide
20071
Objectives
At the end of this class you will:
Understand the basic PICmicro peripherals
and their associated registers
Have HANDS ON experience initializing
Mid-Range peripherals
Be able to implement peripherals not
covered here
Understand interrupts and polling
Write your own application code from
scratch
2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 2
To get the most from this Class
Ideally you should be familiar with the

following:
Assembler programming
Basic Mid-Range family Instruction set
Data and Program memory organization
MPLAB Integrated Development Environment
Microchip ICD2 debugger

201ASP Agenda
Brief review of Mid-Range Architecture,
Instruction Set and Tools
Interrupts on the Mid-Range PICmicro
Interrupts Lab
Peripheral discussion:
Input/Output Ports
Timers
Timer0
Timer1
Timer1 Lab
Timer2
Timer2 Lab

201ASP Agenda (cont.)
Capture / Compare / PWM Module (CCP)
PWM and Output Compare Labs
Analog Comparator
Analog to Digital Converters (ADC)
ADC Lab
Addressable Universal Asynchronous &
Synchronous Receiver & Transmitter (AUSART)
I 2C with the Master Synchronous Serial Port
I2C Based Temp Sensor Lab
Wrap-Up and additional questions
Mid-Range Family Basic
Architecture and
Development Tools
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 JanuarySlide
20076
Mid-Range PIC Block Diagram
STATUS REGISTER
Pages of PROGRAM COUNTER
Program
Memory
8-bit value from instruction
Banks of Data Memory

MUX
ADC
ALU
TIMER0
14-bits
WORKING
AUSART
INSTRUCTION REGISTER REGISTER
MSSP
PERIPHERALS
Program Memory
Maximum Reset Vector 0000h
8K words
(8K x 14 bits/word)/1 byte
= 14Kbytes of memory
Interrupt Vector 0004h
Reset Vector at 0000h 0005h
Page 0 07FFh
Program Counter (PC) will
go to this address on reset 0800h
Page 1 0FFFh
Interrupt Vector at 0004h 1000h

Page 2 17FFh
Program Counter (PC) will
go to this address upon 1800h
any Interrupt Page 3 1FFFh

Program Counter (PC) and Stack
PCLATH
13-bit PC
PCL ALU result (8-bits) or PCH<12:8> PCL PC<12:0>
OPCODE(11-bits) CALL, RETURN,
PCH Paging bits RETFIE, RETLW

Updated from PCLATH Stack Level 1

Specifies page in program
memory
8 Level Deep Stack

Stack Level 8
Stores the contents of the PC

PUSHES
CALL/Interrupt Program Memory
POPS
RETURN, RETFIE,RETLW

Data Memory Map
000h 080h 100h 180h
Special Special SFR 10Fh SFR 18Fh
Function Function 110h 190h
Registers 01Fh Registers 09Fh
020h 0A0h
128
Bytes General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
0EFh 16Fh 1EFh

Shared Shared Shared
07Fh 0FFh 17Fh 1FFh
Bank 0 Bank1 Bank2 Bank3

Special Function Registers (SFRs)
Register File Concept PORTB 06h TRISB 86h
Accessed like any PORTC 07h TRISC 87h

PORTD 08h TRISD 88h
other register PORTE 09h TRISE 89h
PCLATH 0Ah PCLATH 8Ah
Some registers carry INTCON 0Bh INTCON 8Bh
across all banks PIR1 0Ch PIE1 8Ch
(PCLATH, INTCON, etc.) PIR2 0Dh PIE2 8Dh
Bank0 Bank1

Status Register
IRP RP1 RP0 TO PD Z DC C
RP1 RP0
RP1
0 RP0
0 BANK0
0 1 BANK1
Contains: 1 0 BANK2
Arithmetic status of the 1 1 BANK3
ALU
Indirect Register Bank Select bit:
The RESET status
(used for indirect addressing)
Bank select bits for data
memory 1 = Bank 2,3
0 = Bank 0,1

PIC16 Instruction Set
35 single word instructions
All are single cycle except for program branches
Byte Oriented Operations Bit Oriented Operations
addwf f,d Add W and f bcf f,b Bit Clear f
andwf f,d AND W with f bsf f,b Bit Set f
clrf f Clear f btfsc f,b Bit Test f, Skip if Clear
clrw - Clear W btfss f,b Bit Test f, Skip if Set
comf f,d Complement f Literal and Control Operations
decf f,d Decrement f addlw k Add literal and W
decfsz f,d Decrement f, Skip if 0 andlw k AND literal with W
incf f,d Increment f call k Call subroutine
incfsz f,d Increment f, Skip if 0 clrwdt - Clear Watchdog Timer
iorwf f,d Inclusive OR W with f goto k Go to address
movf f,d Move f iorlw k Inclusive OR literal with W
movwf f Move W to f movlw k Move literal to W
nop - No Operation retfie - Return from interrupt
rlf f,d Rotate Left f through Carry retlw k Return with literal in W
rrf f,d Rotate Right f through Carry return - Return from Subroutine
subwf f,d Subtract W from f sleep - Go into standby mode
swapf f,d Swap nibbles in f sublw k Subtract W from literal
xorwf f,d Exclusive OR W with f xorlw k Exclusive OR literal with W
PICmicro Development
Tools
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 Slide
January 200714
MPLAB IDE
MPLAB IDE (Integrated Development
Environment)
Integrates different Microchip and third
party tools
Code Editor
Cross Compilers
Assemblers
Simulators, In-Circuit Debuggers, Emulators
Programmers

ICD 2 (In Circuit Debugger)
MPLAB ICD 2 is a low cost, real-time
debugger and programmer.
Reading/Writing memory space and
EEDATA areas of the PIC
Programs configuration bits
Real time debugging
Erase of program memory
space with verification

PICDEM 2 Plus Board
9V to 5V 16 x 2 LCD
LEDs
regulator Module
RS232
Connecto
r
Analog Pot
18, 28 and 40-

pin DIP
sockets
ICD
Connecto
r
Push button
Switches
Piezo I2C Based
Buzzer Temp Sensor
Interrupts
January 200719
Polling and Interrupts
Often we would like the processor to
perform a task if a specific event occurs
Two methods to check if this event has
occurred:
Polling:
Continuously check for event at various points in
the code
Interrupts:
INTERRUPTS the Main program and starts an
Interrupt Service Routine when an event occurs

Polling
bsf PORTA,1 ;Set bit 1 of
;PORTA RA<1>
RA<1>==11
btfss INTCON,TMR0IF ;Check Timer0

;interrupt flag
;in INTCON
;register and TMR0IF
TMR0IF==11
;skip the next NO ??
??
;instruction if
;it is set YES
goto $-1 ;Go to
;previous RA<1>
RA<1>==00
;instruction
bcf PORTA,1 ;Clear bit 0 of

;PORTA
Interrupts
Reset code 000h no interrupt
goto Start
;========================= Main
Main
int_vector code 004h program
program
execution
execution
Interrupt Service
Routine (ISR) retfie
instruction interrupt flag
retfie ;return from set
;interrupt
;=========================
Execute
ExecuteISR
ISRat
at
main_prog code
address
address004h
004h
Start ;start label for main
code Main program
code
end
Enabling Interrupts
Processor must be told that interrupts

will be used
A number of registers with interrupt enable
bits do this:
Interrupt Control (INTCON)
Peripheral Interrupt Enable 1 (PIE1)

Interrupt Logic
TMR0IE
TMR0IF Interrupt
INTE
INTF
RBIE
RBIF
TMR2IE
TMR2IF
GIE
ADIE
ADIF
Other peripherals
PEIE
INTCON Register
(Core Interrupts)
Enable Bits Description
GIE Global Interrupt Enable Must be set to use
any Interrupts
PEIE Peripheral Interrupt Enable
TMRIE Timer0 Interrupt Enable Must be set to use
INTE External Interrupt Enable any Peripheral
Interrupts
RBIE PORTB change Interrupt Enable
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
Flag Bits Description

Flags will set TMR0IF Timer0 Overflow Interrupt Flag
even if interrupts INTF RB0/INT External Interrupt Flag
arent enabled! RBIF PORTB Change Interrupt Flag
Enabling a Core Interrupt
Int_vect CODE 004h
;clear external interrupt
;flag to enable goto $ address Program Counter
;further interrupts
bcf INTCON,INTF
goto $ address Stack
<ISR code>
retfie
Main CODE INTCON

Start 0 0 0
1 0
1 0 0 0
1 0
<code to set up PORTB >
GIE INTE INTF
; initialize INTCON
clrf INTCON Interrupt detected
;enable an external
;interrupt on the INT pin
on RB0/INT Pin!!
bsf INTCON,INTE
;enable global interrupts

bsf INTCON,GIE
; sit here and loop forever
goto $
Peripheral Interrupts
Two registers ENABLE interrupts for
peripherals
Two registers display peripheral

REQUESTS for an interrupt (Flags)
Peripheral Interrupt Request 1 (PIR1)
Peripheral Interrupt Request 2 (PIR2)
*Flags will set even if

interrupts are not enabled!!
PIE1 and PIR1 Registers*
PIE1 Register (Peripheral Interrupt Enables)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
PIR1 Register (Peripheral Interrupt Requests)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
Enable Flag Condition

ADIE ADIF ADC conversion complete
RCIE RCIF AUSART receive buffer is full
TXIE TXIF AUSART transmit buffer is full
SSPIE SSPIF I2C or SPI Interrupt
CCP1IE CCP1IF Timer1 register capture or compare match
TMR2IE TMR2IF Timer2 value and PR2 period value match
TMR1IE TMR1IF Timer1 register has overflowed
*Check individual datasheets for bit locations

PIE2 and PIR2 Registers*
PIE2 Register (Interrupt Enables)
OSCFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE
PIR2 Register (Interrupt Flags)

OSCFIF C2IF C1IF EEIF BCLIF ULPWUIF CCP2IF
Enable Flag Condition

OSCFIE OSCFIF System Oscillator Failed
C2IE C2IF Comparator2 output changed
C1IE C1IF Comparator1 output changed
EEIE EEIF Write operation completed
BCLIE BCLIF Bus collision occurred in MSSP I2C mode
ULPWUIE ULPWUIF Wake-up condition occurred
CCP2IE CCP2IF Timer1 Capture or Compare match occurred
*Check individual datasheets for bit locations

Enabling a Peripheral (Timer 1)
Int_vect CODE
Interrupt
004h
banksel PIR1 goto $ address Program Counter

bcf PIR1, TMR1IF
<ISR code> goto $ address Stack

retfie
Main CODE INTCON

Start
1 1
0
banksel PIR1
bcf PIR1,TMR1IF GIE PEIE
banksel PIE1
bsf PIE,TMR1IE
PIE1
1
bsf INTCON,PEIE TMR1IE
bsf INTCON,GIE
PIR1
<code to set up Timer1> 0
1
; sit here and loop forever TMR1IF
goto $ Timer1 Overflow!
Interrupt Latency
Interrupt Latency:
Time from interrupt event to execution of
instruction at address 0004h
Synchronous interrupts (typically internal)

latency is 3 instruction cycles (Tcy)
Asynchronous interrupts (typically external)

latency is 3 3.75 instruction cycles

Context Saving
During an interrupt:
Only the PC value is saved (on the stack)
Registers changed in the Interrupt Service
Routine (ISR) are permanently changed
Key registers you may want saved:
Working register
Status
PCLATH (Program Counter Latch High)
User defined registers

Interrupt Priority
Mid-Range PIC microcontrollers treat all
Interrupts with the same priority
The user must do the following:

Determine source of interrupt
Determine the order in which the interrupts
are serviced.

Interrupt Priority Example
INT_VECTOR CODE 0x004 ;interrupt vector
location
;Save context
movwf temp_w ;save WREG
swapf STATUS,w ;movf affects Z bit,
;use swapf instead
movwf temp_status ;save STATUS register
;Check flags in order of priority
btfsc INTCON,RBIF ;PORTB change?
call PORTB_ISR
btfsc PIR1,TMR2IF ;Timer2 interrupt?
call Timer2_ISR
btfsc PIR2,TMR1IF ;Timer1 interrupt?
call Timer1_ISR
Restore_context:
swapf temp_status,w
movwf STATUS ;restore STATUS reg
movf temp_w,w ;restore WREG
retfie ;return from interrupt
Interrupt
Hands on Lab
January 200735
Interrupt
The objective of this is to:

Learn how to set up and enable an interrupt
on the Mid-Range PIC
Become more familiar with the MPLAB IDE,
the PICdem2 Plus and the ICD2
Building a Project
Using the ICD to set a break point

Interrupt Lab Overview
Interrupt Vector Main Program

Call Clear Variables
debounce
delay function Initialize PORTB
(RB0) for S3 input
Increment
Count variable Enable Interrupts
Clear IF No Operation
NOP
Return to Main

Lab Specifics
Code is located in C:\RTC\201_ASP\Lab1-INT

The S3 switch is connected to the RBO/INT
pin on PORTB
The push_count register will display the #
of times S3 has been pushed.
Use MPLAB and the ICD to set a breakpoint
in the code to view the changing value of the
register named push_count

What you need to know
The function of the INTCON register bits
Jumper J6 must be removed in order for
the INTE pin to work
A subroutine called debounce is given
masks the mechanical bouncing of S3
How to setup break points and a Watch
Window in MPLAB

Interrupt Lab Solution
bsf STATUS,RP0 ; point to BANK1

bsf TRISB,0 ; ### initialize PORTB<0> as input
bsf INTCON,INTE ; ### enable INTE interrupts
bsf INTCON,GIE ; ### Enable global interrupts
bcf STATUS,RP0 ; return to BANK0

Peripherals
January 200741
Mid-Range Family Peripherals
I/O Ports
Timers (0, 1, 2)
Capture/Compare/PWM
Comparators
Analog-to-Digital
Converter
AUSART
I2C and SPI Serial
Interface

I/O Overview
Up to 35 bi-directional Input/Output pins
some multiplexed with peripheral functions
High drive capability

25mA source or sink
Direct, single cycle bit manipulation

Most I/Os have ESD protection
After Reset:
Analog capable pins come up as Analog
Digital I/O pins come up as Input

PORTx and TRISx Registers
Every PORT (A, B, C, D, E) will have a
corresponding direction register TRISx
PORTB Register
RB7
RB7 RB6
RB6 RB5
RB5 RB4
RB4 RB3
RB3 RB2
RB2 RB1
RB1 RB0
RB0
Data
Configures Data Direction
PORTB Tri-State Register (TRISB)
TRISB7
TRISB7TRISB6
TRISB6TRISB5
TRISB5TRISB4
TRISB4TRISB3
TRISB3TRISB2
TRISB2TRISB1
TRISB1TRISB0
TRISB0
1 = corresponding PORTB pin is an INPUT

0 = corresponding PORTB pin is an OUTPUT
Configuring Analog Inputs for Digital
I/Os with digital and analog capabilities
default to analog on reset

Two ways to configure Analog inputs as Digital:
1) Analog Select Registers (ANSEL and ANSELH)
For devices with > 8 analog pins
OR
2) ADC Control register 1 (ADCON1)
For devices with 8 or less analog pins
Analog Select Register (ANSEL)

ANS7
ANS7 ANS6
ANS6 ANS5
ANS5 ANS4
ANS4 ANS3
ANS3 ANS2
ANS2 ANS1
ANS1 ANS0
ANS0
Analog Select High Register (ANSELH)

ANS13
ANS13 ANS12
ANS12 ANS11
ANS11 ANS10
ANS10 ANS9
ANS9 ANS8
ANS8
1 = Pin assigned as Analog Input
0 = Digital I/O
ADC Control Register 1 (ADCON1)

Port Configuration Bits
ADFM
ADFM ADCS2
ADCS2 PCFG3
PCFG3 PCFG2
PCFG2 PCFG1
PCFG1 PCFG0
PCFG0
PCFG AN7 AN5 AN4 AN3 AN2 AN1
<3:0> AN6 VddAN0

Port Configuration Bits
ADFM
ADFM ADCS2
ADCS2 PCFG3
PCFG3 PCFG2
PCFG2 PCFG1
PCFG1 PCFG0
PCFG0
Initializing Digital I/O
Initialize PORTB
RB4 through RB7 as Digital Inputs
RB0 through RB3 as Digital Outputs
;------------configure PORTB for digital ----------------------
banksel PORTB ;Go to bank containing PORTB register
clrf PORTB ;Initialize PORTB data
banksel ANSELH ;Go to bank containing ANSELH register
clrf ANSELH ;Set as all digital
;-----------Set up direction of each PORTB pin-----------------

banksel TRISB ;Go to bank containing TRISB register
movlw b11110000 ;Move value to set TRISB<7:4> high and
;TRISB<3:0> low into W register
movwf TRISB ;Move value in W into TRISB

PORTB Interrupt & Weak Pull-Up Options
All PORTB pins have Interrupt-on-Change
and Weak Pull-Up options
Weak Pull-Up PORTB Register (WPUB)
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1
RB3
1 = Pull-up enabled Devices without WPUB register
0 = Pull-up disabled use RBPU bit in OPTION register
Interrupt-On-Change PORTB Register (IOCB)
1 ICOB3 IOCB2 IOCB1 IOCB0
IOCB7 IOCB6 IOCB5 IOCB4
1 = Interrupt-on-change enabled Devices without IOCB rely
0 = Interrupt-on-change disabled on RBIE bit in INTCON
HIGH
RB4
LOW
Interrupt Control Register (INTCON)
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
RBIF
*PORTB must first be read/written and then RBIF can be cleared in software

Timers
January 200750
Timers
Timers are used for many functions:
timing reference to generate an event
count the number of events
waveform generation etc...
PIC16F877 has 3 timers

Timer0
Timer1
Timer2

Timer Comparison
TIMER0 TIMER1 TIMER2
SIZE OF 8-bits (TMR0) 16-bits 8-bits (TMR2)
REGISTER (TMR1H:TMR1L)
CLOCK SOURCE Fosc/4 Fosc/4 Fosc/4
(Internal)
CLOCK SOURCE T0CKI pin T1CKI pin or None
(External ) Timer 1 oscillator
(T1OSC)
CLOCK SCALING Prescaler 3-bits Prescaler 2-bits Prescaler
AVAILABLE (1:21:256) (1,2,4,8) (1:1,1:4,1:8)
(Resolution) Postscaler
(1:11:16)
INTERRUPT On overflow On overflow TMR2 matches
EVENT and FLAG FFh00h FFFFh0000h PR2
LOCATION (TMR0IF in INTCON) (TMR1IF in PIR1) (TMR2IF in PIR2)
CAN WAKE PIC NO YES NO
FROM SLEEP?

Timer 0 Block Diagram
DATA BUS
Fosc/4 8
synchronize
T0CKI
pin
scaled clock TMR0
TMR0
prescaler PS2 PS1 PS0 RATE
Watchdog Timer
WDT out
0 0 0 1:2
0 0 1 1:4
OPTION register
0 1 0 1:8
RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0
0 1 1 1:16
Prescaler Rate Select Bits 1 0 0 1:32
Prescaler Assignment 1 0 1 1:64

TMR0 Clock 1= prescaler assigned to WDT 1 1 0 1:128
Source Select 0= prescaler assigned to Timer 0
1 = TOCK1, 0 = Fosc/4 Source Edge Select 1 1 1 1:256
1 = increment TMR0 on high-to-low transition
0 = increment TMR0 on low-to-high transition
Timer 0 Block Diagram
DATA BUS
Fosc/4 8
synchronize
T0CKI
pin
scaled clock TMR0
prescaler
Watchdog Timer INTCON register
TMR0IF
If the external clock source (TOCKI) is used it will be

synchronized to the internal clock
Timer 0 is readable or writeable
Timer 0 interrupt flag is set on TMR0 roll-over (FF to 00)

Timer0 Initialization
Timer0
;Make sure the Timer0 count incrementing
;register (TMR0) is clear TMR0
banksel TMR0 0
1 0
1 0
1 0
1 0
1 0 0 0
1 1 1
clrf TMR0
INTCON
;Clear Timer0 interrupt flag
bcf INTCON,TMR0IF
0
1
;Setup the Option register to Flag on overflow TMR0IF
;increment Timer0 from internal
;clock with a prescaler of 1:16
This interrupt flag will set on
banksel OPTION_REG Timer0 overflow even if
movlw b00000011 interrupts are disabled
movwf OPTION_REG OPTION_REG
;The TMR0 interrupt is disabled, do 0 0 0 0 0 0 1 1
;polling on the flag bit (TMR0IF)
TOCS PSA
btfss INTCON,TMR0IF
PS<2:0>
goto $-1
Selects Timer 0 Prescaler
Prescaler
Clock Source Assignment
<continue> value = 1:16
(External or Internal) (WDT or TMR0)

Timer1 Block Diagram
T1OSI
T1
OSC
T1OS0 synchronize
prescaler
Fosc/4
T1CKI
TMR1H TMR1L
pin
Enable
Timer1 Control Register (T1CON) TMR1ON

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T1CKPS1 T1CKPS0 scale

1 1 1:8 Timer1 On
1 0 1:4
LP Oscillator Enable 1 = Enable Timer1
1 = T1OSC selected Clock Source Select
0 1 1:2 0 = T1CKI can be used 1 = External (T1CKI)
0 0 1:1 0 = Internal (FOSC/4)

T1OSI
T1
T1OS0 OSC
synchronize
prescaler
Fosc/4
T1CKI TMR1H TMR1L

pin
Enable
Timer1 Control Register (T1CON) TMR1ON
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer1 Gate Enable and Timer1 External Clock Input Synchronization

Timer1 Gate Invert are 1 = do not synchronize external clock input
available on some devices 0 = synchronize external clock input with
internal clock (Fosc/4)

Timer1 Interrupt Setup
TMR1H TMR1L
Main Code
1 0
0
Start 1 01 0 1 0
1 01 0 1 01 1 0
0 1 01 0 1 0
1 0
1 1 0
0 1
;Start by clearing the Timer1 interrupt flag
banksel PIR1
bcf PIR1, TMR1IF PIR1
1
0
;Enable Timer1 interrupt
TMR1IF
banksel PIE1
bsf PIE1, TMR1IE PIE1
1
;Enable Global and Peripheral Interrupts TMR1IE
bsf INTCON, PEIE
bsf INTCON, GIE INTCON
1 1
GIE PEIE

Timer1 Initialization
TMR1H
;Make sure the TMR1 registers are clear 0 0 0 0 0 0 0 0
banksel TMR1H
clrf TMR1H
TMR1L
clrf TMR1L 0 0OVERFLOW!!
0 0 INCREMENTING
TMR1H:TMR1L 0 0 0 0
;Make sure the TMR1IF flag in PIR1
;is cleared
banksel PIR1
bcf PIR1,TMR1IF
PIR1 (Peripheral Interrupt Request)
;Setup T1CON register for internal clock
;with 1:8 prescaler, Timer1 is stopped
0 0 0 0 0 0 0 01
;and T1 osc is disabled
movlw b00110000 TMR1IF
movwf T1CON
T1CON (Timer1 Control)
;Start Timer1 incrementing
bsf T1CON, TMR1ON 0 0 1 1 0 0 0 1
0
;The TMR1 interrupt is disabled, do
;polling on the Timer1 flag bit Input clock
btfss PIR1, TMR1IF prescale bits Timer1 TMR1ON
goto $-1 (T1CKPS<1:0>) oscillator Clock source
enable bit select bit
(T1OSCEN) (TMR1CS)
Timer1 Lab
January 200760
Timer1 Lab
Objective of this lab is to become familiar with

the operation of Timer1
AND
To gain experience enabling Peripheral
Interrupts

Lab Overview
Save Context Initialize PORTB
Clear IF
Initialize Timer1 clock
Reload Timer1
source and pre-scaler:
Timer1 interrupts
every 100,000 Instruction cycles
Toggle LED 0
Enable Timer1, Global

5 Int. ?
th
and Peripheral Interrupts
NO
YES
Toggle LED 3 NOP Main Loop
Restore Context
Retfie
Lab Specifics
The code for the lab is in
C:\RTC\201_ASP\Lab2-TMR1
Within lab2.asm complete the following

Set Timer1 clock source to Fosc/4
Set Timer1 pre-scaler to 2
Load Timer1 with 0x3CB0 (65,536 50,000)
Start Timer1
Enable Timer1, Global and Peripheral Interrupts

Register Operations of INTCON, T1CON,

TMR1H, TMR1L and PIE1
With a value of 0x3CB0 and a pre-scaler of 2,

Timer1 will overflow every 100,000 cycles
The interrupt vector code to toggle the LEDs

has been provided

Timer1 LAB Solution
;*******************************************************************
;Set code to Select clock source, Set pre-scaler to 2, load hex 3CB0
;into Timer1 and turn on Timer1
;*******************************************************************
movlw 0x3C ; ### initialize TMR1L and TMR1H
movwf TMR1H ; ###
movlw 0xB0 ; ###
movwf TMR1L ; ###
bsf T1CON,T1CKPS0 ; ### configure prescaler to 1:2
bsf T1CON,T1CKPS1 ; ###
bcf T1CON,TMR1CS ; ### set clock source to Fosc/4
bsf T1CON,TMR1ON ; ### turn TMR1 on
;
;*******************************************************************
;Enable Timer1 interrupts, Peripheral Interrupts and Global
Interrupts
;*******************************************************************
bsf STATUS,RP0 ; ### point to BANK1
bsf PIE1,TMR1IE ; ### enable TMR1 interrupts
bsf INTCON,GIE ; ### enable Peripheral interrupts
bsf INTCON,PEIE ; ### enable Global interrupts
bcf STATUS,RP0 ; ### return to bank0
Lab Questions
Question:
Was Timer 1 still running during the time it
took to service the Interrupt?
Answer:
Yes
Question:
What effect did this have on the value to be
placed to reload TMR1L and TMR1H?
Answer:
Everything to be precise the latency of
reloading Timer1 should be considered.
TOUTPS3
TOUTPS2 TOUTPS1 TOUTPS0 SCALE
0 0 0 0 1:1
0 0 0 1 1:2
0 0 1 0 1:3 TMR2
0 0 1 1 1:4 OUTPUT
0 1 0
TMR21:5
0
0 Prescaler
1 0 1 1:6
01:1, 1:4,
1 1:16 1 0 1:7
Fosc/4 0 1 1 1 1:8
1 0 0 0 1:9
Postscaler
1 0 0 1
COMPARATOR
1:10
1:1 1:16
1 0 1 0 1:11
1 0 1 1 1:12
1 1 0 PR2 1:13
0
1 1 0 1 1:14
1 1 1 0 1:15
1 1 1 1 1:16
Timer2 Control Register (T2CON)

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
T2CKPS1 T2CKPS2 Scale

0 0 1:1 Timer2 ON
0 1 1:4 1 = Timer2 enabled
1 X 1:16
Start Timer2
Counting TMR2
OUTPUT
TMR2
Prescaler
1 1 1 1 0
1 1
0 0
1 1
0
Fosc/4
1:1, 1:4, 1:16
Postscaler
COMPARATOR 1:1 1:16
PR2
Load Period PIR1
Register 1 1 1 1 1 0 0 0
1
TMR2IF
Timer2 Control Register (T2CON)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Flag set on first

match with
postscaler = 1:1

Timer2 Initialization Timer2
Incrementing
TMR2 (Timer2 Counter)
;Disable the Timer2 interrupts in the PIE1
;register. Make sure the Timer2 interrupt 0
1 0
1 0
1 0
1 0
1 0
1 0 1
1 0
;flag in PIR1 is cleared.
banksel PIE1 PR2 (Period Register Timer2)
bcf
banksel
PIE1,TMR2IE
PIR1
1 0 0 0 0 0 0 0
bcf PIR1,TMR2IF PIE1 (Peripheral Interrupt Enable)
;Setup T2CON register for Postscaler = 1:15,
;Prescaler = 1:16, Timer2 off 0
movlw b01110010 TMR2IE
movwf T2CON PIR1 (Peripheral Interrupt Request)
;Make sure the TMR2 register is clear
banksel TMR2 1
0
clrf TMR2 TMR2IF
;Load the Period register Flag is set
banksel PR2
movlw b10000000 T2CON (Timer2 Control)
movwf PR2
;Start Timer2 incrementing 0 1 1 1 0 0
1 1 0
banksel T2CON
bsf T2CON,TMR2ON
;The Timer2 interrupt is disabled, do TMR2ON
;polling on the Timer2 interrupt flag Postscaler = 1:15
btfss PIR1,TMR2IF (TOUTPS<3:0>) Prescaler = 1:16
goto $-1 (T2CKPS<1:0>)
Timer2 Lab
January 200771
Timer2 Lab
The Goal of Lab 3 is to become familiar with
the following:
Timer2 Clock Source
Setting the Prescaler
Setting the Postscaler
Turning on Timer2
Setting the Interrupt Enable bits needed for
Timer2 to successfully generate an interrupt.

Lab Overview
Save Context Initialize PORT B
Set up Timer2
Increment counter the Period,
number of times Prescaler,
Timer2 has interrupted Postscaler
Output 3 LSBs of count

Enable interrupts
to LEDs
NOP
Restore context
retfie

Lab Specifics
Code for this lab is in
C:\RTC\201_ASP\Lab3-TMR2
Complete the following sections of code
Set Timer2 prescaler to a value of 4
Set Timer2 postscaler to a value of 13
Turn Timer2 on
Configure the GIE and PEIE bits in the Interrupt
Control register (INTCON)
Configure the Timer2 Interrupt Enable bit in the
Timer2 Configuration register (T2CON)

Special Function Registers (SFRs)
needed for this lab are:
INTCON(Interrupt Control)
PIE1..(Peripheral Interrupt Enable 1)
PR2...(Timer2 Period Register)
T2CON..(Timer2 Control)
With the Period register (PR2) set to 250,
the prescaler at 4, and the postscaler at
13, Timer2 will interrupt every 13 ms
(about 1/80 second) with a 4Mhz oscillator
(Fosc/4 = 1Mhz).
Timer2 Lab Solution
;*****************************************************************
; configure Timer2 prescaler of 4, PR2 of 250 and a postscaler
; of 13 and turn timer2 on.
;*****************************************************************
;
BANKSEL T2CON ; point to bank containing T2CON
movlw 0x60 ; ### set TMR2 postscaler = 1:13
movwf T2CON ; ###
bsf T2CON,T2CKPS0 ; ### set TMR2 prescaler = 1:4
bsf T2CON,TMR2ON ; ### turn on TMR2
;*****************************************************************
;Enable Timer2 interrupts, Peripheral and Global Interrupts
;*****************************************************************
bsf STATUS,RP0 ; point to BANK1

bsf PIE1,TMR2IE ; ### enable TMR2 interrupts
bsf INTCON,PEIE ; ### enable peripheral interrupts
bsf INTCON,GIE ; ### enable global interrupts

Lab Questions
Question:
Like Timer1, does Timer2 keep running
during Interrupt latency?
Answer:
Yes it does!
Question:
Does the user have to account for the free
running Timer2 in order to ensure a precise
interrupt period?
Answer:
No, Interrupt occurs on match not overflow
Capture/Compare/PWM
Module
January 200778
Capture/Compare/PWM
Capture
(CCP) Overview
Times the duration of an external event using an
inputCCP
pin MODE Timer Resource
Compare
Capture Timer 1
Changes an output pin or generates an interrupt
Compare Timer 1
when a specific amount of time has passed
Pulse PWM
Width Modulation (PWM) Timer 2
Creates a reconfigurable, steady duty-cycle, square
wave output at a defined frequency
Provides enhanced features for various bridge
connectivity
* Module interfaces with Timers 1 and 2

CCP Control Register
CCP1 Control Register (CCP1CON)
P1M1 P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPxM
3
BITCCPxM2 CCPxM1 CCPxM0 CCP Mode Selected
FUNCTION
0 0 CCP Mode
0 Select0 Bits configure the module asoffInput
Capture/Compare/PWM (resetsCapture,
CCP module)
CCP1M<3:0>
0 0 Output
0 Compare,1or PWM Unused (reserved)
0CCP1<X:Y>
0 PWM1duty cycle 20 LSBs (8 MSBs located
Compare intoggle
mode, CCPR1L)
output on match
0 0 1 1 Unused (reserved)
0 1
These0 PWM output0
configuration bits are available for Enhanced
Capture mode, every falling edge
P1M<1:0> CCP (ECCP) modules only. They provide half-bridge or full-bridge
0 1 0 1 Capture mode, every rising edge
output steering control.
0 1 1 0 Capture mode, every 4th rising edge
0 1 1 1 Capture mode, every 16th rising edge
1 0 0 0 Compare mode, set output on match
1 0 0 1 Compare mode, clear output on match
1 0 1 0 Compare mode, generate software interrupt on match
1 0 1 1 Compare mode, trigger special event
1 1 x x PWM mode

Capture Mode
Prescaler CCPxIF in PIRx
1, 4, 16
CCPx
TMR1H TMR1L
CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE
Edge Detect
0 1 0 and 0 Capture every falling edgeBuffered
Single
0 1 0 1 Capture every rising edge
0 1 1 0 Capture every 4th rising edge
System Clock (Fosc)
0 1 1 1 Capture every 16th rising edge
CCPRxH CCPRxL
CCPxCON

Capture Initialization
TMR1H
;Turn off CCP module
CCP1 0 0 0 0 0 0 0 0
banksel CCP1CON Pin
clrf CCP1CON TMR1L
;Make sure Timer1 is off
0
1
bcf T1CON,TMR1ON 4
3
TIMER1
0 0 INCREMENTING!!
0 Current Timer1
0 0 0Value0 0
21th
rd
nd
st
;Clear Timer1 registers Rising Edge CCPR1H
clrf TMR1H
Detected!!
clrf TMR1L
;Disable all interrupts for CCP CCPR1L
bcf PIR1,CCP1IF
banksel PIE1 Captured!
bcf PIE1,CCP1IE PIR1
;Set CCP1 pin for input
bsf TRISC,2
0
1
;Set Capture for every 4th rising edge CCP1IF
banksel CCP1CON CCP1CON
movlw b00000110 0 0 0 0 0 10 0 1 0
movwf CCP1CON
;Start Timer1 incrementing
bsf T1CON,TMR1ON T1CON
;Test the interrupt flag for capture 1
0
btfss PIR1,CCP1IF
goto $-1 TMR1ON
Compare Mode
TMR1H TMR1L
CCPxIF in PIRx
COMPARATOR
COMPARATOR NO
CCPxM3 CCPxM2
Does CCPxM1 CCPxM0 MODE
Does
TMR1H:TMR1L =
1 TMR1H:TMR1L
0 0= 0 Set output onOUTPUT
OUTPUT
match (CCPxIF is set)
CCPRxH:CCPRxL
CCPRxH:CCPRxL YES CCPx
LOGIC
LOGIC
1 0 ??
?? 0 1 Clear output on match (CCPxIF is set)
Generate software interrupt on match
1 0 1 0
(CCPxIF is set CCP1 pin unaffected)
Trigger special event
1 0 1 1 (CCPxIF is set, CCP1 resets TMR1 or
CCPRxH CCPRxL TMR2 and starts an A/D conversion if
enabled)
Special Event Trigger

Compare Initialization TMR1H
;Turn off the CCP module
banksel CCP1CON 0 0 0 0 0 0 0 0
clrf CCP1CON
;Turn off Timer1 TMR1L
0TMR1H:TMR1L = 1000 0000 0000 0000
bcf T1CON,TMR1ON
;Clear Timer1 result registers TIMER1 0 INCREMENTING!!
0(CCPR1H:CCPR1L
0 0 Value)
0 0 0
clrf TMR1H
clrf TMR1L CCPR1H
;Disable CCP1 interrupt and make sure
;its flag is clear
banksel PIE1
1 0 0 0 0 0 0 0
bcf PIE1,CCP1IE CCPR1L
banksel PIR1
bcf PIR1,CCP1IF 0 0 0 0 0 0 0 0
;Make CCP1 pin output
banksel TRISC
bcf TRISC,2 T1CON
;Initialize Compare to set output on match
banksel CCP1CON 0
1
movlw b00001000
movwf CCP1CON TMR1ON
;Load Compare value into CCPR1H:CCPR1L CCP1CON
banksel CCPR1H
movlw b10000000 0 0 0 0 1
0 0 0 0
movwf CCPR1H
clrf CCPR1L
;Start Timer1 incrementing PIR1
bsf T1CON,TMR1ON
;Test CCP1IF for Timer1 match with CCPR1x 0
1
btfss PIR1,CCP1IF
goto $-1 CCP1IF
PWM Mode
Generates a Pulse-Width Modulated
(PWM) signal on the CCP1 and CCP2 pins
Duty cycle, period and resolution
determined by the following registers
Register Description
PR2 Period Register
T2CON Timer2 Control
CCPRxL 2 Duty Cycle Registers
CCPxCON 2 CCP Control Registers

PWM Block Diagram
Period 1 Period 2
CCPR1L
DUTY CYCLE VALUE
CCP1<X:Y>
DOUBLE 10
BUFFER
CCPR1H LATCH
10
Period CCP1 Output Pin
TMR2 = CCPR1H
COMPARATOR Start
10 R
Latch
TMR2incrementing
TMR2 Reset to 0s (1) 0
1
8 S CCP1
pin
COMPARATOR
TMR2 = PR2
8 Note (1): TMR2 is concatenated with the

2-bit FOSC, or 2-bits from Prescaler
PR2 to create 10-bit time base
PWM Initialization
TMR2
;Turn off CCP1 pin by setting TRISC bit HIGH 0 0 0 0 0 0 0 0
banksel TRISC
bsf TRISC, 2 ;configure pin as input PR2
;Clear Timer2 0 1 1 1 1 1 1 1
banksel TMR2
clrf TMR2 CCPR1L
;Set up Period and Duty Cycle

0 0 0 1 1 1 1 1
movlw b01111111 ; CCP1CON
movwf PR2 ;Load a Period Value
movlw b00011111 ; 0 0 1 0 1 1 0 0
movwf CCPR1L ;Load Duty Cycle Value
;Configure CCP module for PWM duty cycle PWM Mode

;and LSBs of Duty Cycle = b10 LSBs CCP1M <3:0>
movlw b00101100 CCP1<X:Y>
movwf CCP1CON T2CON
;Turn CCP1 pin back on (make it an output) 0 0 0 0 0 1 0 0

banksel TRISC
bcf TRISC,2 Prescaler bits Prescaler bits
;Start the PWM by turning on Timer2
TOUTPS<3:0> T2CKPS<1:0>
;Configure Prescaler and Postscaler to 1:1)
movlw b00000100 TMR2ON
movwf T2CON

Pulse Width Modulation
(PWM) Lab
January 200792
PWM Lab Objectives
Become familiar with the CCP module

configuration and operation in PWM mode
Gain additional exposure to Timer2
configuration

PWM Lab Overview
The PWM waveform is output on the
CCP1 pin (RC2) that will emit a tone on
the PICdem2 plus onboard buzzer.
When the lab is completed, a 50% duty

cycle at a period of 256/(Fosc/4) will
drive the buzzer.

PWM Lab Overview
Main Code
Load PR2 value
Set up RC2 as output pin
Load CCPR1L for 50% duty cycle
Configure CCP as 8-bit PWM
Turn on Timer2 w/ 1:1 pre scaler
NOP

PWM Lab Specifics
Code for the lab is in
C:\RTC\201_ASP\Lab4-PWM
Complete the following sections
Configure PORTC pin 2 ( CCP1) as an output
Set CCP in PWM mode
Clear CCP1X and CCP1Y (8-bit PWM)
Configure Timer2 with 1:1 pre-scaler

The code to load PR2 (Timer2) and to set a
50% duty cycle has been provided. These
values can be seen in the code
The CCP1 pin is RC2 (Pin 2 of PORTC) on
the PIC16F877
Registers needed to complete this lab are:
TRISC
T2CON
CCP1CON
PWM Lab Solution
;*****************************************************************
; Set CCP1 as an output
;*****************************************************************
bcf TRISC,2 ; ### config CCP1 pin PORTC<2> as output
bcf STATUS,RP0 ; point to BANK0

movlw 0x80 ; establish duty cycle @ 50%
movwf CCPR1L
;*****************************************************************
; Put CCP1 module in PWM mode.
;*****************************************************************
movlw 0x0C ; ### configure CCP for PWM

movwf CCP1CON ; ###
;*****************************************************************
; Configure Timer2 pre and post scale of 1:1 and turn Timer2 on
;*****************************************************************
bsf T2CON,TMR2ON ; ### turn on TMR2

PWM Lab Questions
Question:
Why didnt we have to enable the interrupts
for the PWM to work?
Answer:
PWM will run concurrently with the PICmicro
MCU without slowing the processor down

Output Compare
Lab
January 100
2007
Output Compare Lab
Goals of the lab are to gain experience with
the following:
Setting up the CCP for Output Compare
Configure the Special Event Flag to reset Timer1
Configure the CCP to generate an Interrupt on
Timer1 overflow
Using an Interrupt Vector to modify the interval
between Interrupts
Compare Lab Overview
This lab configures the CCP into output compare
mode driven by Timer1
An Interrupt is used to change the sound of the
buzzer
During the Interrupt Service Routine (ISR):
The RC2/CCP1 pin (connected to buzzer) is toggled
The ISR period is reduced:

The Compare Register (CCPR1L) is decremented

The Timer1 count registers are reset
The combination of a reduced period and the

CCPR1L roll-over will cause the buzzer to emit a
chirping sound
Compare Lab Overview
Save Context Configure CCP as
Output Compare
Clear IF
Initialize Timer1
Toggle CCP
Output Pin
Initialize PORT C
Drives
Buzzer Decrement
CCPR1L
Turn on timer1
Reset
Timer1 NOP
RETFIE
Compare Lab Specifics
The code for this lab is in
C:\RTC\201_ASP\Lab5-CCP
Complete the following sections:
Configure the CCP as an Output Compare
that sets the Special Event Flag and CCP1IF
Configure Timer1 with a clock source of
Fosc/4 and a pre-scaler of 1:8
Configure Special Function Registers to
allow the CCP interrupt to occur
The registers needed to complete this lab are:
INTCON (Interrupt Control)
T1CON (Timer1 Control)
CCP1CON (CCP1 Control)
PIE1 (Peripheral Interrupt Enable)
The Interrupt Vector has been provided

The Value of CCPR1L will rollover from 0 to
0xFF and continue to decrement
Compare Lab Solution
;
; Set CCP1CON to Output Compare mode with Special Event Trigger
; to clear the Timer 1 register pair on a match
;****************************************************************
movlw 0x0B ; ### value for CCP1CON
movwf CCP1CON ; move to CCP1CON
;
; Configure Timer 1 for Fosc/4 operation. 8:1 Prescaler
;
;****************************************************************
movlw 0x30 ; ### value for TMR1
movwf T1CON ; ### move to TMR1 control register
;
; Enable Timer 1 interrupts, Peripheral Interrupts and
; Global Interrupts
;****************************************************************
bsf PIE1,CCP1IE ; ### enable CCP1 interrupt
bsf INTCON,PEIE ; ### enable peripheral interrupts
bsf INTCON,GIE ; ### enable global interrupts
Lab Question
Question:
The PWM did not require an interrupt in order
to work. Do we need an interrupt to operate in
output compare mode?
Answer:
Not necessarily
Peripherals always set their associated interrupt
flag, so you have the choice of polling or directly
responding to the interrupt.
The choice is based on the need of your
application.
Comparators
January 108
2007
Comparator Overview
Comparator Module:
Compares analog input voltage to a reference
and outputs a digital result
Vref
V in
Analog Input
(Vin) Output
+ (Vout)
Comp
Reference Voltage
(Vref)
-
V out
Comparator Reference Voltage
Voltage Reference can be either:
External from a device pin
Internally generated with the Voltage Reference
Module

Provides 16 selectable voltages from 0 to 75% of VDD
Some devices can also scale VREF+ and VREF-

Some devices also have a fixed reference (0.6V)
Independent of VDD
VREF+
VRSS = 1 VRR
8R R R R R
VRSS = 0
V 15 8R
CVREFDD
To Comparators VREF-
and ADC Module 0 VRSS = 1
CVREF 4 VR<3:0>
VRSS = 0
VROE VREN
Comparator Interrupts
An Interrupt occurs when the
comparator output changes
Some devices share one flag for both
comparators
Some devices have independent flags
Must read the comparator output before
clearing interrupt flags
Outputs found in the comparator control
register (CMCON or CMxCON0)
Resets the output mismatch condition
Comparators and Sleep Mode
Comparators remain active in Sleep

A Comparator output change will wake-up
core
After wake-up, the instruction following

the SLEEP instruction or an Interrupt
Service Routine (ISR) is executed
Analog-to-Digital
Converter (ADC)
January 113
2007
ADC Overview
Analog-to-Digital Converter Module
Converts analog input signal into an 8 or 10-bit
binary value
Selectable internal or external reference voltage
Interrupt can be generated after conversion is
completed

The interrupt can wake the PICmicro from SLEEP
ADC
Analog Digital
Input Output
ADC Control Registers
The ADC implements two control registers
ADCON0 and ADCON1
Devices with > 8 analog inputs do not have same bits
shown below

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON
BIT FUNCTION
ADCS<1:0> A/D Conversion Clock Select bits
Use with ADCS2 in ADCON1
CHSx bits Analog Channel Select bits
GO/DONE 1 = A/D Conversion in progress

0 = A/D Conversion is completed
ADON Enables the ADC module
ADC Control Registers
The ADC implements two control registers
ADCON0 and ADCON1
Devices with > 8 analog inputs do not have same bits
shown below

ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0
BIT FUNCTION
ADFM ADC Result Registers Format bit
1 = Right Justified, 0 = Left Justified
ADCS2 A/D Conversion Clock Select bit
Use with ADCS<1:0> in ADCON0
PCFG<3:0> Port Configuration Bits
Configures I/O as analog or digital
ADC Result Registers
10 bit ADC result in is placed in two registers
ADRESH and ADRESL
Left or Right Justified
Determined by Format Select bit (ADFM) in ADCON1 register
ADRESH ADRESL
MSB LSB
Left Justified (ADFM = 0)

ADRESH ADRESL
MSB LSB
Right Justified (ADFM = 1)

ADC Module Diagram
PCFG AN7
<3:0> AN6 AN5 AN4 AN3 AN2 AN1
VddAN0
Conversion
Port Config Bits Fosc clock scaler
AN0 VREF+
AN1 pin
AN2 Start Conversion
AN3 Conversion Complete
AN4 ADC
AN5
AN6 00000011 11111111
AN7 Holding ADRESH ADRESL
Capacitor Left Justified Right Justified
VREF-
pin
ADCON0
ADCS1 ADCS0 CHS2
0 0
CHS1 0
CHS0 0
1
GO/DONE ADON
Vss
ADCON1
0
ADFM
1 ADCS2 PCFG3 PCFG2 PCFG1 PCFG0
Timing Considerations for ADC
When an A-to-D channel is selected
time must be taken for the holding
capacitor to charge
All 10 bit conversions take 11 cycles to
complete
User must select the appropriate ADC
clocking based on the system clock
frequency
Analog-to-Digital
Conversion LAB
January 121
2007
ADC Lab
This Lab will familiarize you with:
Setting up the ADC module
Operating a peripheral from the Main
program, not an interrupt vector
Using the value read from one peripheral
(ADC) to drive another peripheral (CCP in
PWM mode)
ADC Lab Overview
Main Program
Configure Timer 2
Configure PORT C
Configure CCP for

PWM
Configure and
Turn on ADC
Enable interrupts
Continued on
next page
ADC Lab Overview (cont.)
Continued from
Previous Page
Main Loop NO
TMR2IF=1
YES
Start ADC
NO
ADC done?
YES
Put ADC value in
CCPR1L
Output 4 LSBs of
ADC value to LEDs
ADC Lab Specifics
in the project C:\RTC\201_ASP\Lab6-ADC
Configure the ADC to return a left justified
value
Set ADC Conversion Clock to FOSC/32
Turn on ADC unit
Complete the code to start an ADC and wait
for the conversion to finish in the main
control loop
This lab does not do the ADC conversion in

an interrupt routine. We will use a polling
method.
Writing the value of the ADC conversion into
CCPR1L will change the duty cycle of the
buzzer
ADCON1 and ADCON0 special function
registers are used to complete this lab
ADC Solution
;*************************************************************************
; Configure ADC: Channel 0, left justified, Tad = 8 * Tosc, turn on ADC
;*************************************************************************
clrf ADCON0 ; ### ensure default channel is set to channel 0
bsf ADCON0,ADCS1 ; ### set Tad = Fosc/4
bsf ADCON0,ADON ; ### turn on ADC
bsf STATUS,RP0 ; ### point to BANK1
movlw 0x0E ; ### left justify, configure AN0 analog
movwf ADCON1
;
; Enable Timer 2 interrupts, Peripheral Interrupts and Global Interrupts
;
bsf PIE1,TMR2IE
bsf INTCON,GIE
bsf INTCON,PEIE
;
;*************************************************************************
; add three lines of code to start the ADC conversion and wait for the
; conversion to complete
;*************************************************************************
bsf ADCON0,GO ; ### start ADC conversion
btfsc ADCON0,GO ; ### Is the conversion done?
goto $-1 ; ### no: loop until done
ADC Lab Question
Question:
Instead of waiting for TMR2IF to be set in
the main program, could we start the ADC
from within an interrupt routine?
Answer:
YES
ADDRESSABLE Universal
Synchronous Asynchronous
Receiver Transmitter
(AUSART)
January 129
2007
AUSART Overview
Serial I/O communications peripheral
Sometimes called Serial Communications
Interface (SCI)
Main Functions:
Can be synchronous or asynchronous
Can receive and transmit

Full-duplex asynchronous transmit and receive

Half-duplex synchronous master and slave
Most common use
RS-232 communications to a PC serial port

Needs driver for RS-232 level shifter
Enhanced (EUSART) features allow interface
with a Local Interconnect Network (LIN) bus
system
AUSART Registers
Baud rate generator registers
SPBRG (8 bit for AUSART)
SPBRG and SPBRGH (16 bit for EUSART)
Transmit status and control
TXSTA
Receive status and control
RCSTA
Transmit data register
TXREG
Receive data register
RCREG
TXSTA Register
CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D
Bit Function
CSRC Clock Source Select
1 = Master Mode (clock generated internally from BRG)
0 = Slave Mode (clock from external source)
TX9 Ninth bit transmission enable
TXEN Transmit Enable bit, 1 = Tx enabled, 0 = Tx disabled
SYNC AUSART Mode , 1 = Synchronous Mode, 0 = Asynchronous Mode
SENB For EUSART only
1 = Send sync break character bit
0 = Sync break transmission is completed
BRGH Baud Rate Select, 1 = High Speed, 0 = Low Speed
TRMT Transmit Shift Register (TSR) status
1 = TSR empty, 0 = TSR is full
TX9D Ninth bit of transmit data
RCSTA Register
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
Bit Function
SPEN Serial Port Enable
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
RX9 1 = Enable 9-bit data reception, 0 = 8-bit data

SREN Synchronous mode (Master), 1 = enable single Rx, 0 = disable single Rx
CREN Continuous Receive Enable, 1 = enable, 0 = disable
ADDEN Address Detect Enable bit
1 = enable (enable interrupt and load the Rx buffer when RSR<9> is set)
0 = disable and use 9th bit for parity
FERR 1 = framing error occurred (Stop bit not detected)

OERR 1 = Overrun error occurred (FIFO was still full when other data was
loaded)
RX9D Ninth bit of received data
Transmit Block Diagram
DATA BUS TXIE

TXREG Interrupt
TXIF
Set TXIF Clear TXIF

MSB LSB
TXEN Pin Buffer TX/DT
and Control
Transmit Shift
pin
Register (TSR) SPEN
Enables Serial
Baud Rate
Generator
Port
TRMT
TX9D TX9
Set TRMT bit
Ninth data bit Indicates shift register is empty
Clear TMRT bit
TSR has data in it
Receive Block Diagram
Enable Serial Port
SPEN
Receive Shift Register (RSR)

RX/DT Pin Buffer Data STOP START
pin and Control Recovery
RX9
Baud Rate FIFO

Generator
Set RCIF flag
Clear RCIF flag RCREG
RCIE RCIF
RX9D
Interrupt Data Bus
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
January 136
2007
MSSP Overview
The MSSP module can operate in one of two modes:
SPI (Serial Peripheral Interface)

3 pins are used
Serial Data Out (SDO)
Serial Data In (SDI)
Serial Clock (SCK)
I2C (Inter-Integrated Circuit)

Full Master mode

Slave mode (with general address call)

2 pins are used
Serial Clock (SCL)
Serial Data (SDA)
The MSSP Control Register (SSPCON) determines

which mode you are in.
We will cover I C mode only 2

I2C Conditions
Conditions :
SDA
START (S)
SDA pulled
released
LOW
while SCL is
SCL still HIGH
STOP (P)
Recipient
StopSDA
condition
goes
doesLOW
quickly
not drive
during
followed
SDA
by a9Start
LOW th
clock
condition
pulse of SCL
ACKNOWLEDGE (A)
RESTART (R)
NEGATIVE or NOT-ACKNOWLEDGE (N)

External IC EEPROM Read +5V
SCL
MASTER
SDA
READ
WRITE
GOTO
STOP
MODE
DATA
ADDRESS
BUSY BUSY
PIC
LISTEN LISTEN LISTEN
EEPROM
EEPROM
SLAVE
START
RESTART
STOP
ACK
NACK
MEMORY SLAVES ACK
DATA
ADDRESS
ADDRESS
MSSP Control Registers
(I2C mode)
1 of 3: MSSP Status Register (SSPSTAT)
SMP CKE D/A P S R/W UA BF
CONTROL BITS DETECTION BITS (FLAGS)
BIT FUNCTION
SMP Slew Rate Control bit
CKE Not used in I2C mode
D/A Last byte Rx/Tx was data or address
P Stop Condition Detected
S Start Condition Detected
R/W Slave :READ/WRITE or Master = transmit in progress
UA Address needs to be updated
BF The SSPBUF register is full
SSPM3
0
SSPM2
0
SSPM1
0
SSPM0
0
(I
Mode
2
C mode)
SPI Master mode, clock = FOSC/4
0 0 0 1 SPI Master mode, clock = FOSC/16
0
2 of 3:
0
MSSP
1
Control
0
Register 1 (SSPCON)
SPI Master mode, clock = FOSC/64
0 0 WCOL1 SSPOV
1 SSPEN CKP mode,
SPI Master SSPM3
clockSSPM2 SSPM1 SSPM0
= TMR2 output/2
0 1 0 0
CONTROL BITSSPI Slave mode, DETECTION
clock = SCK pin, SS pin control enabled
BITS (FLAGS)
0 1 0 1 SPI Slave mode, clock = SCK pin, SS pin control disabled,
BIT FUNCTION
SS can be used as I/O pin
0 WCOL
1 1 0 Write
I2C Slave mode,Collision Detected
7-bit address
0 1
SSPOV 1 A 1write to I2C
theSlave mode, 10-bit
SSPBUF before address
previous value processed
1 0 0 0 I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
SSPEN Enables MSSP module
1 0 0 1 Reserved
1 CKP
0 1 0 Reserved Enables clock
1 SSPM3
0 1 1 Mode Select
I2C firmware controlled MasterBit
mode (Slave idle)
1 1
SSPM2 0 0 Reserved
1 1
SSPM1
0 1 Mode Select bits
Reserved
1 1 1 0 I2C Slave mode, 7-bit address with Start and Stop bit
SSPM0 interrupts enabled
1 1 1 1 I2C Slave mode, 10-bit address with Start and Stop bit
interrupts enabled
(I2C mode)
3 of 3: MSSP Control Register 2 (SSPCON2)
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
CONTROL BITS DETECTION BITS (FLAGS)
BIT FUNCTION
GCEN Generates an interrupt when a call is received (slave mode)
ACKSTAT 0 = Acknowledge received from slave (transmit mode)
ACKDT 0 = ACK 1 = NACK (receive mode)
ACKEN Initiate ACK/NACK condition (Transmits ACKDT bit)
RCEN Enables receive mode
PEN Initiates a STOP condition
RSEN Initiates a RESTART condition
SEN Initates aa START
Initiates START condition
condition
Tx/Rx Buffer (SSPBUF)
Buffer register containing Tx and Rx data
SSPBUF interfaces to a shift register (SSPSR) for
shifting data in or out
When full, the Buffer Full (BF) bit in the

SSPSTAT register is set
Any write to the SSPBUF register during
Tx/Rx of data will be ignored, and the write
collision detect bit (WCOL) of the SSPCON
register will be set
I C Address Register
2
(SSPADD)
Slave mode:
Contains the slave address of the PIC
Compared against the received value
Master mode:
Used to calculate the clock speed
(BAUD rate) of the I2C system.
Fosc
BAUD RATE =
4 ( SPADD 1)
*NOTE: FOSC is the frequency of the oscillator

not the Instruction Clock TCY
MSSP Interrupts
The MSSP interrupt flag (SSPIF) is set in
the PIR1 register with the following events:
START condition
STOP condition
Tx or Rx complete
Acknowledge transmit
RESTART condition
I2C Based Temp Sensor
Lab
January 149
2007
I2C Based Temp Sensor
Lab Objective
Configure some MSSP control registers to
enable I2C communication to the I2C based
Temp sensor on the PICDEM 2 Plus board.
Temperature reading (lowest 4 bits) will be
displayed on the LEDs.
I2C Lab Overview
This lab configures the MSSP as an I2C
Master
The TC74 Temperature Sensor is then
read by the MSSP module
The temperature reading is then sent to
PORTB to be displayed on the 4 LEDs
I2C Lab Overview
Main
Code
Configure I/0s
Configure MSSP
Initiate I2C start condition
Send Temp Sensor Address

Loop
Read Temperature
Display Temp LSB

on PORTB LEDs
I2C Lab Specifics
Code for the lab is in
C:\RTC\201_ASP\Lab7-I2C
Complete the following sections:
Disable the slew rate control
Well be using I2C standard rate (100KHz)
Configure the MSSP to operate as an I2C
master and enable the data (SDA) and
clock (SCL) pins
Start the data transfer and check for
when it has completed
Slew rate control is found in the
SSPSTAT register
Registers needed to complete this
lab are:
SSPSTAT
SSPCON
SSPCON2
I2C Lab Solution
;--------------------------------------------------------------
; set the slew rate and baud rate for 100 MHZ operation
BANKSEL SSPSTAT ; ### point to correct BANK for SSPSTAT

bsf SSPSTAT,SMP ; ### Set for standard speed slew rate
;--------------------------------------------------------------
; Configure as I2C master with Fosc/4 Clock source
BANKSEL SSPCON
bsf SSPCON,SSPM3 ; ### set to I2C master mode with
; Fosc/4 clock source
bsf SSPCON,SSPEN ; ### Enable SDA and SCL pins to
; operate in I2C mode
;--------------------------------------------------------------
BANKSEL SSPCON2 ; Initiate a START condition

bsf SSPCON2,SEN ; ### set the SEN bit
btfsc SSPCON2,SEN ; ### is it finished?
goto $-1 ; no: test again
Multiple Interrupt
Lab
January 156
2007
Multiple Interrupts Lab
This Lab involves:
Dealing with 2 (or more) concurrent interrupts
Determining the source of an interrupt
Deciding which interrupt request will be
serviced first
Lab Overview
Main Program
Set up CCP as Output
Compare just as in Lab 6
Enable Timer1 and

PORTC as In Lab 6
Setup PORTB and enable

External Interrupts on
S3as in Lab 1
NOP
Continued on next slide
Lab Overview
Interrupt Service Routines
INT_ISR CCP_ISR
Call debounce Clear IF
Delay routine
Put -1 in WREG
Toggle variable
Called push_fla
push_flag g
Set ?
Clear IF Put 0 in WREG
Add WREG to
Return to Main CCPR1L
Return to Main
Lab Overview (cont.)
Save
context
Interrupt Handler
Did CCP NO
generate the
interrupt?
YES Did INT generate

the interrupt?
NO
Go to CCP YES
service routine Service
External
Interrupt
Return to Main
Lab Specifics
Lab is found in:
C:\RTC\201_ASP\Lab8-MXINT
The two Interrupt Service Routines (ISRs)

are provided:
INT_ISR
CCP_ISR

When an interrupt occurs, determine the cause
and transfer control to the appropriate ISR
Set the Special Function Registers (SFRs) to
enable INT and CCP1 Interrupts to occur
What you need to know for Lab
INTCON, and PIR Special Function

Registers are used in this lab
Lab Solution
Int_Service_Routine
call save_regs; ; save W, STATUS, & PCLATH
btfsc INTCON,INTF ; ### test for INTE interrupt request

goto INTE_ISR
btfsc PIR1,CCP1IF ; ### test for CCP interrupt request
goto CCP_ISR
Finish_Int ; restore W, STATUS & PCLATH
call Restore_Regs
retfie
Lab Solution ( cont.)
bsf PIE1,CCP1IE ;### enable CCP1 interrupt

bsf INTCON,INTE ;### enable INTE interrupt
bsf INTCON,GIE ;### enable global interrupts
bsf INTCON,PEIE ;### enable peripheral interrupts
Lab Questions
Question:
Why is there a noticeable silence when S3 is
pushed?
Answer:
Since debounce is called during an interrupt
and the GIE bit is cleared, the CCP1 interrupt that
toggles the buzzer is not allowed to operate.
Therefore, the buzzer goes quiet.
Lab Questions (cont.)
Question:
How can this silence be eliminated and the
buzzer continue to run?
Answer:
1. Capture S3 in Main and call debounce
while GIE is set
2. Use a timer to accomplish the delay
3. Re-enable interrupts during the INT ISR
201ASP Wrap-Up
January 167
2007
Peripherals Class Wrap-up
Today we covered the following
peripherals on the Mid-Range family
I/O ports
Interrupt structure and processing
Timers (timer0, timer1, timer2)
CCP Module ( Output Compare, Input Capture,
PWM)
Comparators and Analog-to-Digital Converters

Voltage Reference
AUSART Serial Port
I2C using the MSSP module
Final Word
This discussion has followed the standard
Microchip datasheet flow:
Overview of Peripheral Use these sections to:
Develop logical flow charts or
pseudo-code (Avoid Spaghetti
Register Description Programming!!)
and Configuration
Other Tips:
Comment your code thoroughly
Enhanced or Choose descriptive names
Special Features for user defined registers
*Packaging and Electrical Specifications are at the end

of the datasheet
Resources
Visit www.microchip.com for:
24/7 technical support
Application Notes
Web Seminars
Code examples
Datasheets
and Much More!
Thank You!!
January 171
2007

201 - ASP v8.0

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201ASP

Mid-Range Family Peripheral

Ideally you should be familiar with the

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 3

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 4

8-bit value from instruction

Banks of Data Memory

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 8

8 Level Deep Stack

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 9

0EFh 16Fh 1EFh

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 10

Register File Concept PORTB 06h TRISB 86h

Accessed like any PORTC 07h TRISC 87h

across all banks PIR1 0Ch PIE1 8Ch

(PCLATH, INTCON, etc.) PIR2 0Dh PIE2 8Dh

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 11

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 12

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 16

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 17

18, 28 and 40-

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 20

btfss INTCON,TMR0IF ;Check Timer0

bcf PORTA,1 ;Clear bit 0 of

Processor must be told that interrupts

Peripheral Interrupt Enable 2 (PIE2)

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 23

GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF

Flag Bits Description

Main CODE INTCON

;enable global interrupts

Two registers display peripheral

*Flags will set even if

PIR1 Register (Peripheral Interrupt Requests)

Enable Flag Condition

*Check individual datasheets for bit locations

PIR2 Register (Interrupt Flags)

Enable Flag Condition

*Check individual datasheets for bit locations

banksel PIR1 goto $ address Program Counter

<ISR code> goto $ address Stack

Main CODE INTCON

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 31

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The user must do the following:

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 33

The objective of this is to:

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 36

Interrupt Vector Main Program

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 37

Code is located in C:\RTC\201_ASP\Lab1-INT

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 38

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 39

bsf STATUS,RP0 ; point to BANK1

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2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 42

High drive capability

Direct, single cycle bit manipulation

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 43

1 = corresponding PORTB pin is an INPUT

2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 45

Analog Select Register (ANSEL)

Analog Select High Register (ANSELH)