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Andrew Brown
Jonathan Warner
Laura Strickland
Table of Contents
Applications of ADCs
Types of ADCs
Successive Approximation Example
The ADC on the MC9S12C32
Analog to digital converters convert analog, or real world
signals to a series of 1s and 0s, able to be stored or
transmitted through computers or digital systems.
Introduction cont.
Reasons why this would be needed:
Digital storage of a non-digital signal
(ex: recording light intensity of a lightning strike using sensors, mapping
a flight path of an aircraft onto a computer for analysis)
Transmitting data over a digital system
(ex: sending your voice through a telephone system, Skype chatting,
Analog Signals
Analog signals are the smooth, real, signals of the world.

These signals can contain any and all values needed to

represent the data in question.
Digital Signals
Digital signals, however, contain series of discrete values,
with interpolation occurring between data points to
recreate the signal.

Digital signals are meant to be used in digital systems,

and therefore are composed simply of 0s and 1s.
Benefits of Digital Signals over Analog
Can be stored in digital system.
Can be compressed.
Can filter out frequencies you dont want, analog noise is
How does it work?
ADCs work in two steps:
Lets look again at our last graph:

Our discrete values on the y axis are taken at spaced-out

time steps on the x axis.
These are the sampling points.
Sampling cont.
Larger number of
sampling points during
the same amount of Nyquist Theorem:
time = smoother Sampling rate should
looking graph. be 2*highest frequency
you want to capture.
Sampling rate is this
frequency at which
sampling will occur.
Sampling Question
If you use a sampling rate of 50,000 Hz for 2 seconds,
how many data points are you capturing?

What is the distance between each point on the resulting

graph of Voltage vs. time?
Sampling for y axis

Assigning a binary
code value to discrete
measurements, stored
on a fixed-length
Quantization Noise
Since values are rounded to the nearest possible digital
value, a certain level of quantization noise will occur.
Example: In an 8-bit resolution system, a value of 236.4
will be stored as the digital value 236.

Signal to noise ratio measures the noise level by the

SNR = 6.02*n + 1.761 dB, for n-bit resolution
Disadvantages of Digital

Not a perfect representation

of the analog signal
Example: Phone
Low memory systems give
systems use a sampling
rate of 8kHz, so all
you bad quality output, as
frequencies above 4kHz
are canceled. As a resolution or sampling may
result, playing music
through a phone sounds
muffled and low quality.
be low
Aliasing occurs when a signals frequency is above the
Nyquist Frequency.

The data points captured suggest a lower frequency

signal than the one that actually exists.
Sound recording
ADCs are used to convert sound waves into digital
signals through the use of computer microphones or

This allows digital storage and transmission of music,

voice, and other sound data.
Ex: Telephones convert your voice using 8kHz sampling.
Sensors and Data Acquisition
Digital sensors output an analog voltage when reading
light sensors
pressure sensors

Computers store this data by converting the signal to

digital values, used later by computers.
Digital Cameras
Photo-sensors on
cameras convert
photon impacts into
voltage outputs.
These are then
converted to digital
values and stored on
your cameras memory
card to be recreated
later on a computer.
Circuit representation of ADC
The general representation of an ADC is shown below.

But what is inside the ADC block? How is the data

recorded and stored?
Jonathan Warner
1. Parallel Design (Flash)
2. Successive Approximation
3. Dual-Slope
4. Sigma-Delta
Parallel Design (Flash ADC)
Vref set to Vmax
Resistors used to divide reference
voltage into intervals
Comparators used to compare Vin to
the reference voltages
Encoder uses logic gates to convert
control logic to binary digital output

2^n-1 comparators
Parallel Design (Flash ADC)

Advantages Disadvantages
Fastest ADC 2^n-1 comparers
(gigahertz) Low resolution
Simple Design Large Die size
Can achieve Prone to glitches
non-linear output (out of sequence
Successive Approximation
DAC-Based Design

Starts by setting MSB D(n-1)

to 1
Uses DAC and op amp to
determine if bit should
remain 1 or be set to zero
(greater or less than Output Buffer allows the circuit
Vres * 2^(n-1)) to read the digital data while the
Next, bit D(n-2) set to 1 and ADC is working on the next
comparison is repeated
Successive Approximation
DAC-Based Design

Advantages Disadvantages
Speed, worst case
Resolution tradeoff
n clock cycles with speed
Conversion time
independent of
amplitude of Vin
Capable of outputting
the binary number in
serial (one bit at a time)
Integrator-Based Design
Switch connects Vin with
Switch held for fixed
number of clock cycles
Analog switched at set time
to Vref
T2 clock cycles
proportional to Vin
Vin = Vref x T2/T1
Integrator-Based Design
Integrator-Based Design

Advantages Disadvantages
Insensitive to Speed, 2^n-1 clock
components value cycles
Limited applications
Can achieve high
resolution (but at the
cost of speed)
Useful for highly
Analog signal set to
Resulting sawtooth
waveform compared with
zero volts
Output either high or low
Clock rate used is very high,
Output converted to positive or results in oversampling of data
negative Vres and fed back to be
added to next samples Vin
Resulting stream of 0s and 1s
represents the analog signal
average voltage

Advantages Disadvantages
High Resolution Speed,
No need for precision Oversampling
components Only applicable for
low bandwidth
ADC Comparison

Type Speed Cost Resolution

(relative) (relative)
Dual Slope Slow Med 12-16
Flash Very Fast High 4-12
Successive Medium Low 8-16
Approx Fast
Sigma Slow Low 12-24
Successive Approximation
Given: Find:
Bit Voltage
8 bit ADC n bit digital 7 1
Vin = 0.2 V output 6 0.5
Vref = 2 V 5 0.25
4 0.125
3 0.0625
2 0.03125
2n = 28 = 256 1 0.015625
Vres = Vref / 256 0 0.0078125
Vres = 0.0078125 V (Resolution)
Successive Approximation
Example (cont.)
1 0 0 0 0 0 0 0 0.4 < 1

0 1 0 0 0 0 0 0 0.4 < 0.5

0 0 1 0 0 0 0 0 0.4 > 0.25

0 0 1 1 0 0 0 0 0.4 > 0.375

0 0 1 1 1 0 0 0 0.4 <0.4375

0 0 1 1 0 1 0 0 0.4 <0.4063

0 0 1 1 0 0 1 0 0.4 > 0.39

0 0 1 1 0 0 1 1 0.4 > 0.398

0 0 1 1 0 0 1 1 Digital
The ATD10B8C on the MC9S12C32

Input Pins
MC9S12C32 Block Diagram
The Basics of the ATD10B8C
Resolution: 8- or 10-bit (manually chosen)
8-channel multiplexed inputs
Successive Approximation architecture
Can perform single or continuous sampling
Can sample single or multiple channels
Conversion time: 7 s (in 10-bit mode)
Optional external trigger
ATD10B8C Block Diagram
Pin Purposes
AN7/ Analog input channel
PAD7 External trigger for
General purpose
digital I/O
AN6/PAD6 Analog input/
AN0/PAD0 General purpose
digital I/O
VRH, VRL High, low reference
VDDA, VSSA Supply power for analog
Control Register 2

Pin Description

7 0 Power down ATD; has recovery time period

1 Normal ATD functionality
6 0 Normal clearing (read CCF before reading result register)
1 Fast Flag Clearing (auto-clear CCF after result register is
5 0 Continue running in Wait Mode
1 Halt conversion and power ATD down while in Wait Mode
4 0 External Trigger Edge
1 Trigger Level
3 0 Low/falling trigger polarity
1 High/rising trigger polarity
2 0 Disable external trigger mode
1 Enable external trigger mode
1 0 ATD Sequence Complete Interrupt Request disabled
1 ATD Sequence Complete Interrupt Request enabled
0 0 No ATD interrupt occurred
1 ATD sequence complete interrupt pending
Control Register 3

Pin Description
6-3 Controls the number of conversions per sequence
2 0 ATD Conversion calculation goes to
corresponding result register
1 Current ATD conversion put in consecutive result
registers; wraps around sequentially at end
1-0 Determines how ATD responds to a breakpoint (see
Table 8.5)
Control Register 4

Pin Description
7 0 10-bit resolution
1 8-bit resolution
6-5 Selects the length of the second phase of the
sample time in units of ATD conversion clock
cycles. (See Table 8-7)
4-0 ATD Clock Prescaler (PRS) (5 bits long). ATD
conversion clock frequency is calculated by:
ATDclock = * 0.5
PRS +1
Control Register 5

Pin Description
7 0 Data in the result registers is left-justified
1 Data in the result registers is right-justified
6 0 Result register data is unsigned
1 Result register data is signed
5 Continuous Conversion Sequence Mode
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
4 Multi-Channel Sample Mode
0 Sample only one channel
1 Sample across multiple channels
2-1 Selects the analog input channel(s) whose signals are
sampled and converted to digital codes (See Table 8-12)
Single Channel (MULT = 0)
Single Conversion (SCAN = 0)

7 6 5 4 3 2 1 0 ATDDR5


Port AD
Result ATDDR2
Interface ATDDR1
ATD Converter ATDDR0
Single Channel (MULT = 0)
Continuous Conversion (SCAN = 1)

7 6 5 4 3 2 1 0 ATDDR5

Port AD
Result ATDDR2
Interface ATDDR1
ATD Converter ATDDR0
Multiple Channel (MULT = 1)
Single Conversion (SCAN = 0)

7 6 5 4 3 2 1 0 ATDDR5

Port AD
Result ATDDR2
Interface ATDDR1
ATD Converter ATDDR0
Single Channel (MULT = 1)
Continuous Conversion (SCAN = 1)
7 6 5 4 3 2 1 0 ATDDR5


Port AD
Result ATDDR2
Interface ATDDR1
ATD Converter ATDDR0
Status Register 0

Pin Description
7 0 Conversion sequence not completed
1 Conversion sequence completed (set to 1 after each
sequence complete when SCAN mode is on)
5 0 No external trigger overrun error has occurred
1 External trigger overrun error has occurred
4 0 No overrun in results
1 A overrun in results
3-0 Conversion Counter (read-only; points to result register that
will receive the result of the current conversion)
Status Register 1

Pin Description
7-0 Conversion complete flag (one bit is set at the end
of every conversion in a conversion sequence,
going from CCF0 in order to CCF7)
0 Conversion # x is not completed
1 Conversion # x is completed and results are
Left-Justified Result Register

Right-Justified Result Register is similar.

Each register has a high and a low byte.
8 Result Registers total ($0090 - $009F)
Setting Up the ATD
Step 1: Power-up the ATD and define settings in ATDCTL2
ADPU = 1 powers up the ATD
ASCIE = 1 enables interrupt

Step 2: Wait for ATD recovery time (~ 20s) before


Step 3: Set the number of successive conversions in

S1C, S2C, S4C, S8C determine the number of conversions (see Table 8-4)
Setting Up the ATD
Step 4: Configure the resolution, sampling time, and ATD
clock speed in ATDCTL4
PRS0, PRS1, PRS2, PRS3, PRS4 set the sampling rate (see Table 8-6)
SRES8 sets the resolution to 8-bit (= 1) or 10-bit (= 0)

Step 5: Configure the starting channel, single/multiple

channel, SCAN setting and whether result data should be
signed or unsigned in ATDCTL5
CC, CB, CA determine input channel (see Table 8-12)
MULT sets single (= 0) or multiple (= 1) inputs
SCAN sets single (= 0) or continuous (= 1) sampling
DJM sets output format as left-justified (=0) or right-justified (=1)
DSGN sets output data as unsigned (=0) or signed (=1)