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You are on page 1of 25

Lecture 24

Announcements

Homework 8 due today

Exam 3 on Tuesday, 11/25.

Topics for exam are up on the course webpage.

Agenda

Last time:

Master-Slave Flip-Flops (6.4)

Edge-Triggered Flip-Flops (6.5)

Characteristic Equations (6.6)

This time:

Registers (6.7)

Counters (6.8-6.9)

Review

Registers

A collection of flip-flops taken as an entity.

Function: Hold information within a digital system so

that it is available to the logic elements during the

computing process.

Each combination of stored information is known as

the state or content of the register.

Shift register: Registers that are capable of moving

information upon the occurrence of a clock-signal.

Unidirectional

bidirectional

Registers

Two basic ways in which information can be

entered/outputted

Parallel: All 0/1 symbols handled simultaneously. Require as

many lines as symbols being transferred.

Serial: Involves the symbol-by-symbol availability of

information in a time sequence.

Four possible ways registers can transfer information:

Serial-in/serial-out

Serial-in/parallel-out

Parallel-in/parallel-out

Parallel-in/serial-out

Serial-in, Serial-out, Unidirectional Shift

Register

Serial-in, Parallel-out Unidirectional Shift

Register

Parallel-in, Parallel-out Unidirectional Shift

Register

Universal Shift Register

A bidirectional shift register. Capable of shifting contents either left or right depending upon the

signals present on appropriate control input lines.

Universal shift register: Depending on the signal values on the select lines of the multiplexers, the

register can retain its current state, shift right, shift left or be loaded in parallel. Each operation is

the result of a positive edge on the clock line.

Counters

An example of a register.

Primary purpose is to produce a specified output

pattern sequence.

Also called a pattern generator

Each stored 0/1 combination is called the state of the

counter.

The total number of states is called its modulus.

If a counter has m distinct states then it is called a mod-m

counter.

The order in which states appear is referred to as its

counting sequence.

Depicted by a directed graph called a state diagram.

State Diagram of a Counter

denotes one of the states of the counter.

Arrows in the graph denote the order in which

the states occur.

Binary Ripple Counters

Counters whose counting sequence

corresponds to that of the binary numbers are

called binary counters.

Modulus is , where is the number of flip-flops

in the counter.

Binary up-counter, binary down-counter

4-bit Binary Ripple Counter

Recall positive edge-triggered T-Flip-Flop.

Each positive transition from logic-0 to logic-1

causes the flip-flop to toggle.

4-bit Binary Ripple Counter

4-bit Binary Ripple Counter

Known as a ripple counter since a change in the state of the flip-

flop is used to toggle the flip-flop.

The effect of a count pulse must ripple through the counter.

Ripple counters also referred to as asynchronous counters.

Propagation Delay

There is a propagation delay between the input and output of a flip-flop.

Rippling behavior affects the overall time delay between the occurrence

of a count pulse and when the stabilized count appears at the output

terminals.

Worst Case?

Going from to since toggle signals must propagate through the entire

length of the counter.

For n-stage binary ripple counter, the worst case time is , where is the

propagation delay time associated with each flip-flop.

Synchronous Binary Counters

All flip-flops change simultaneously after the

appropriate propagation delay associated with

a single flip-flop.

Count pulses are applied directly to the

control inputs, C, of all the clocked flip-flops.

All flip-flops change simultaneously after the

appropriate propagation delay associated with a

single flip-flop.

Synchronous Binary Counters

Output of AND gate preceding the th flip

if all lower-order bits are in 1-state. If yes,

flop consists of the inputs fo the and-gate

toggles on positive clock edge.

preceding the st flip-flop and the output

Drawback: And gates have many inputs.

Mod-m Counter

Use a mod- counter as a mod- counter.

Load an initial binary number prior to the counting

operation.

Counter structure is modified to allow for parallel

loading.

JK flip-flops are used instead of T flip-flops.

Two enable signals:

Load enable: Allows parallel loading of data inputs

Count enable: allows for counting.

Mod-m Counter

signals: One to allow parallel loading

of the data inputs and a second for

counting. Operations synchronized

with positive edges of the count

pulses. The load function takes

precedence over the count function

(due to NOT-gate connected to the

load enable line).

Mod-10 Counter

8-bit Counter

from 2 4-bit counters.

Counters Based on Shift Registers

Ring counter. Not efficient in the number of flip-flops used, but provides a

decoded output. To detect any particular state in the counting sequence it is only

necessary to interrogate the output of a single flip-flop.

Counters Based on Shift Registers

Twisted ring counter. The complement of the rightmost flip-flop serves as the

input to the leftmost flip-flop. states occur in the counting sequence of an -stage

counter.

Underlined pairs of bits uniquely determine a state. A single two-input and-gate is

required to obtain a decoded output.

Always has even number of states.

Counters Based on Shift Registers

Twisted ring counter for odd number of states. The state consisting of all 1s is

eliminated from the counting sequence. Achieved by connecting to the input of

the leftmost D flip-flop.

Each state is detectable by use of a single two-input and-gate.

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