# Introduction to Computer Engineering Lecture 9: Combinational Logic, Mixed Logic

Logic circuits
 Combinational

N inputs

Combinational circuits

M outputs

 Sequential

inputs

outputs Combinational circuits

Storage Element delay

N inputs

Combinational circuits

M outputs

 

Outputs, “at any time”, are determined by the input combination When input changed, output changed immediately
 Note that real circuits are imperfect and have “propagation

delay”

A combinational circuit
 Performs logic operations that can be specified by a set of

Boolean expressions  Can be built hierarchically
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X0 X1 X2 X3 X4 X5 X6 X7 X8

9-input Odd Function 9-input Odd Function Z
X0 X1 X2 X3 X4 X5 X6 X7 X8 A0 3-input A1 B0 A2 Odd

Function

Function Specification: To detect odd number of “1” inputs, i.e. Z=1 when there is an odd number of “1” present in the inputs

A0 3-input A1 B0 A2 Odd

Function

A0 3-input A1 A2 Odd

Z

Function

A0 3-input A1 B0 A2 Odd

Function

How to design a 3-input Odd Function?

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A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 0 1 1 0 1 0 0 1 A BC 00
0 1 0 1 01 1 0 11 0 1 10 1 0

F = A BC + ABC + A BC + ABC = A(BC + BC) + A(BC + BC) = A(B ⊕ C) + A(B ⊕ C) = A ⊕ (B ⊕ C) = A⊕B⊕C

X0 X1 X2 X3 X4 X5 X6 X7 X8

9-input Odd Function 9-input Odd Function Z
X0 X1 X2 X3 X4 X5 X6 X7 X8 A0 3-input A1 B0 A2 Odd

Function

A0 3-input A1 B0 A2 Odd

Function

A0 3-input A1 A2 Odd

Z

Function

3-input Odd function: B0=A0 ⊕A1⊕A2

A0 3-input A1 B0 A2 Odd

Function

A0 A1 A2
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B0

F(A, B, C, D) = BC + A D
B C A D F

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 Enable  Allow

component reuse

a digital logic circuit designer to implement a combinational logic with
 Only NAND gates  Only NOR gates  Only NAND and NOR gates

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9

 Implement

all ORs in the Boolean

function  Implement all ANDs in the Boolean function  Forget all the inversion at this moment

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F(A, B, C, D) = BC + A D
B C A D

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 Draw

“Vertical Bars” in the circuits where all complements in the Boolean equation occur a bubble on each Vertical Bar

 Draw

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F(A, B, C, D) = BC + A D
B C A D

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 Convert each gate to the desired gate  If only NAND gate is available, insert a

bubble in front of the AND gate  If only OR gate is available, insert a bubble in front of the OR gate

 Using DeMorgan’s Law in the process  OR ⇒ NAND: by adding 2 bubbles on the

inputs side of OR  AND ⇒ NOR: by adding 2 bubbles on the inputs side of the AND

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F(A, B, C, D) = BC + A D
Assume this design uses NAND gates only
B C A D

= =
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 Balance

the bubbles on each wire, i.e. even out the number of bubbles on every wire  If there is odd number of bubbles on a wire, add an inverter (i.e. a bubble)  And remove those “vertical bars with bubbles” which are used to help only, not in the circuits
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F(A, B, C, D) = BC + A D
Assume this design uses NAND gates only
B C A D

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Inverters can be implemented by either a NAND or a NOR gate
 Wiring the inputs together

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F(A, B, C, D) = BC + A D
Assume this design uses NAND gates only
B C A D

F(A, B, C, D) = BC + A D
Assume this design uses NAND gates only
B C A D

6 NAND gates are used

 How

about build the prior circuits with only NOR gates?

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F(A, B, C, D) = BC + A D

B C A D

F(A, B, C, D) = BC + A D

B C A D

Add vertical bar for each inversion

F(A, B, C, D) = BC + A D
Assume this design uses NOR gates only
B C A D

= =

Convert each gate to a NOR
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F(A, B, C, D) = BC + A D
Assume this design uses NOR gates only
B C A D

Balance number of Bubbles on each wire
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F(A, B, C, D) = BC + A D
Assume this design uses NOR gates only
B C A D

Balance number of bubbles on each wire and substitute all gates to NOR
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F(A, B, C, D) = BC + A D
Assume this design uses NOR gates only
B C A D

7 NOR gates are used

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F = A + B + C + A (B + C ⋅ D))
C D B A

Implement the logic circuits by ignoring all inversions
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F = A + B + C + A (B + C ⋅ D))
C D B A

Add vertical bar/bubble for each inversion
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F = A + B + C + A (B + C ⋅ D))
C D B A

Assume this design uses NAND gates only
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F = A + B + C + A (B + C ⋅ D))
C D B A

Balance the bubbles for each wire w/ inverters
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F = A + B + C + A (B + C ⋅ D))
C D B A

Remove the vertical bars/bubbles
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F = A + B + C + A (B + C ⋅ D))
C D B A

Replace all the gates to NAND gates
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F = A + B + C + A (B + C ⋅ D))
C D B A

Final mixed logic uses 11 NAND gates (one of them is a triple-input NAND gate)
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B D A C

F = A CA BD

Implement the logic circuits by ignoring all inversions
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B D A C

F = A CA BD

Add vertical bar/bubble for each inversion
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B D A C

F = A CA BD

Assume this design uses NOR gates only
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B D A C

F = A CA BD

Balance the bubbles for each wire w/ inverters
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B D A C

F = A CA BD

Remove the vertical bars/bubbles
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B D A C

F = A CA BD

Replace all the gates to NOR gates
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B D A C

F = A CA BD

Final mixed logic uses 9 NOR gates
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