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ELX215/EAT237

HARDWARE

PowerPoint Slides
by Manimaran
Learning Outcome(s)

1. To know the history of micrprocessors.

2. To know the microprocessor system terms.

3. To understand different types of micrprocessors.

4. To know the advantages of microprocessor systems.

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Learning Objective(s)

1. To know the scope of microprocessor systems in the


field of Engineering.

2. To know the history and advantages of building


microprocessor based systems.

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Software 004: Exception Processing
Execution States
Privilege States

Changing the Privilege State

Exception Processing

Multiple Exceptions

Special Exceptions

Exception Handlers

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Execution States
Three states:
Normal:
Executing user instructions.

Halted:
Caused by system failure.

Invoked by user by invoking a system halt (assert the line).

Exception:
Caused by system failure

Caused by special program errors

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Changing of States:

- After entering the exception processing state, the 68K may:


o Execute some special instructions, then return to the normal state.
o Enter the halted state from the exception state.

Example:
- A divide-by-zero caused the processor to enter the exception state.

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(pg 105} [1]
Figure 4.1: An exception occurring during normal program execution

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Privilege States
2 States:
User State
Supervisor State
Provides a sense of security for designers of operating systems, or
complex programs that deal with user programs.

Privileged instructions:
Instructions for overwriting/ changing important memory locations.
May be executed only in the supervisor state.
Users are restricted from privileged instructions.

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System Stack:

User Stack:
User Stack Pointer (USP)

Supervisor Stack:
Supervisor Stack Pointer (SSP)

Used when S-bit is set


Executing Exception Code
Executing Privileged Instruction


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Figure 4.2: 68K SR (pg 106) [1]

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Privileged Instructions:
STOP
RESET
RTE
Move to SR
AND immediate to SR
EOR immediate to SR
OR immediate to SR
MOVE USP

RTE excluded from execution in the user state.


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Assigning SSP for all protected memory references
does not accomplish memory security.
User may still access protected memory locations.
Protection is required at the hardware level
Example:
In the figure on the next page, the simplified block
diagram shows how access to user and supervisor
memory sections can be controlled via the
processors FC2 states bit.

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(pg 107) [1]
Figure 4.3: User/Supervisor memory partitioning

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Changing the Privilege State
Changing from User to Supervisor State: Invoking Exceptions
Interrupt
Illegal Instruction
Bus Error etc

Exception Setup:
Save current contents of the status register
Set S-bit high

Changing from Supervisor to User State:


RTE (from exception)
MOVE SR, ANDI SR, EORI SR to clear S-bit


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Example:
To clear the S-bit in the SR while leaving all other bits
unaffected:

AND SR

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Exception Processing Sequence
Processing an exception usually involves these four steps:
1. The contents of the status register are saved and the S bit is
set so that the 68K may enter the supervisor state.
2. The exception vector is obtained.
3. The program counter and status register are saved on stack.
4. Execution resumes at the address specified in the exception
vector.

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Step 1: Adjusting Status Register

- Copy of the status register is made

- S bit is set to enter the supervisor state.


- T bit is cleared to stop Trace Exception.

- If Reset or Interrupt exception:


o SRs Interrupt Mask (bits 8-10) are also updated.

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Step 2: Get Vector Number
- Exceptions are referred to by vector numbers:
o 8-bit numbers

o Determined by processor or supplied by external circuitry.

Most are determined internally by the Processor.

o Ranges from 0 to 255 (00 to FF)

- Vector Numbers point to 4-byte block memory location containing


addresses of Exception Handler routines (1st kb of 68k memory)
- The addresses for the exception handlers are stored with the high word
first, followed by the low word.
- To get the address on vector table, vector no. should be times by 4.

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(pg 110) [1]
Table 4.1: Exception Vector Assignments

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Example:
Consider the instruction DIVU D4, D5. Register D4
contains zero at execution time.

- Divide-by-zero exception, vector 5 is invoked.

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Step 3: Save Processor Information

- For all exceptions (except Reset), current PC and SR are saved onto the system
stack.

- SSP is used because the processor is in the supervisor state.

(pg 111) [1]


Figure 4.4: Exception stack contents

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Step 4: Fetch New Program Counter

- New PC is fetched from memory location pointed by exception vector.


- Normal processing (in the supervisor state) then resumes at new


address.

- Exception code must end with an RTE to return the processor to the
task it was running before the exception occurred.

- The addresses for the exception handlers are restored with the high
word first, followed by the low word.


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Example:
A user writes code for a divide-by-zero exception handler
and places the routine at 7A238. The exception vector
table must be filled in the following way: Addresses 014
and 015 must contain 0007 (the high word of the starting
address), and locations 016 and 017 must contain A238
(the low word of the starting address). Even though the
68ks address bus is only 24 bits wide, the address must
occupy 32 bits in the vector table. This is accomplished by
making the upper 8 bits 0.

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Figure 5.14: Software-controlled queue structure (pg 159) [1]

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References

Antonakos J.L., The 68000 Microprocessor, Hardware


and Software Principles and Applications, 1993, Prentice
Hall, New Jersey.
Clements A., Microprocessor Systems Design, 68000
Hardware, Software, and Interfacing, 1992 PWS-KENT
Publishing, Massachusetts.

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Key Terms:
Term Definition
CPU Generally refers to the microprocessor

RAM Rewrite memory chip

EPROM Non-erasable memory used to store start up programs

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