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# AUDISANKARA COLLEGE OF ENGINEERING

AND TECHNOLOGY
BATCH NUMBER B01

## NAME OF STUDENT ROLL NUMBER

1. M.MADHAN KUMAR 14G21A0479
2.S.KAVYA 14G21A04B7
3.E.SAI RAM 14G21A04E4
4.R.MANOJ KUMAR 14G21A04A5
5.G.KISHORE KUMAR 15G21A0404
DOMAIN
VLSI DESIGN TECHNOLOGY

SUB DOMAIN
LOW POWER AND AREA EFFICIENT
CONTENTS
ABSTRACT
INTRODUCTION
EXISTING SYSTEM
PROBLEM IN EXISTING SYSTEM
SOLUTION OF THE PROBLEM
SIMULATION
C0NCLUSION
ABSTRACT
Carry select adder is one of the fastest adders used in many data
processing processors to perform fast arithmetic function.
By gate level modification of CSLA architecture we can reduce area
and power.
Based on this modification 16-bit squareroot csla (SQRT CSLA)
architecture been devoleped.
The proposed design has reduced area and power as compared with
regular SQRT CSLA.
This work evaluates the performance of the proposed designs in
terms of area,power by hand with logical effort and through Xilinx ISE
14 .2 (VERILOG HDL) and this will be implemented in FPGA.
INTRODUCTION

## In electronics,an adder or summer is a digital circuit that performs

Adders can be constructed for many numerical reprasentations ,such
as BCD or Excess-3,the most common adders operate on binary
numbers.
Adders plays major role in multiplication and other advanced
processers designs.
EXISTING SYSTEM
The carry-select adder generally consists of two ripple carry adders
(RCA) and a multiplexer.

Adding two n-bit numbers with a carry-select adder is done with two
adders (therefore two RCA).

## In order to perform the calculation twice ,one time with the

assumption of carry being zero and other assuming one.
PROBLEMS IN EXISTING SYSTEM
The problem in CSLA design is the number of full adders are
increased then the circuit complexity also increases.

The number of full adder cells are more thereby power consumption
of the design also increases

Number of full adder cell doubles the area of the design also
increased.
SOLUTION OF THE PROBLEM
The only solution of the problem present in the carry select adder
(CSLA) is the parallel ripple carry adder(RCA) with Binary-Excess 1
converter(BEC)
SIMULATION
The tools used for simulation are
PROGRAMMING LANGUAGE :VERILOG HDL
TOOL: Xilinx ISE(10.2)
APPLICATIONS
Arithmetic and logic units.