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EENG447

Digital IC
Design

Dr. Gürtaç Yemişcioğlu


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CHAPTER #3
PHYSICAL DESIGN

Stick Diagrams

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STICK DIAGRAMS
VDD
VDD

x f ? x x’

GND

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STICK DIAGRAMS
VDD
VDD

x x’
x f

GND

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STICK DIAGRAMS
VLSI design aims to translate circuit concepts onto silicon.

Stick diagrams are a means of capturing topography and layer information


using simple diagrams.

Stick diagrams convey layer information through colour codes (or monochrome
encoding).

Acts as an interface between symbolic circuit and the actual layout.

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STICK DIAGRAMS
Does show all components/vias.
– Via is used to connect higher level metals from metal connection

It shows relative placement of components.

Goes one step closer to the layout

Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

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STICK DIAGRAMS
Does not show
– Exact placement of components

– Transistor sizes

– Wire lengths, wire widths, tub boundaries

– Any other low level details such as parasitics

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STICK DIAGRAMS
CMOS PROCESS LAYERS
Metal 4

Metal 3

Metal 2

Metal 1

n+ (n-diff)

p+ (p-diff)

polysilicon

contact

via

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STICK DIAGRAMS
SOME RULES

Rule 1.

When two or more ‘sticks’ of the


same type cross or touch each
other that represents electrical
contact.

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STICK DIAGRAMS
SOME RULES

Rule 2.

When two or more ‘sticks’ of


different type cross or touch each
other there is no electrical
contact.

(If electrical contact is needed we have to


show the connection explicitly).

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STICK DIAGRAMS
SOME RULES

Rule 3.

When a poly crosses diffusion it


represents a transistor.

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STICK DIAGRAMS
SOME RULES
Rule 4.
In CMOS a demarcation line is drawn
to avoid touching of p-diff with
n-diff. All pMOS must lie on one
side of the line and all nMOS will
have to be on the other side.

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STICK DIAGRAMS
SOME RULES
Rule 5.
Metal 1 should be part of the contact.

pdiff and ndiff cannot touch. Impossible

Long interconnects must be metal

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STICK DIAGRAMS
Series and Parallel Connections
A B
A B

n+ n+ n+ n+ n+ n+

A B
A B
x x

n+ n+ n+ n+ n+ n+

y y

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STICK DIAGRAMS
CMOS Inverters
VDD VDD

GND GND

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STICK DIAGRAMS
CMOS NAND
VDD VDD

P1 P2

f
x1 N1 x1
F
x2 N2 x2

x1
x2 f
GND

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STICK DIAGRAMS
CMOS AND
VDD VDD

P1 P2 P3

f
x1 N2 N1 x1
F
x2 N3 x2

x1
x2 f
GND

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STICK DIAGRAMS
CMOS NOR
VDD VDD

x1 P1

x2 P2 x1
f F
N2 N1 x2

x1
x2 f
GND

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STICK DIAGRAMS
CMOS OR
VDD VDD

x1 P1

x2 P2 P3 x1
f F
N2 N1 N3 x2

x1
x2 f
GND

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STICK DIAGRAMS
Complex Circuits
F = A’+(B’+C’)D’
CD
VDD
A B C D F AB 00 01 11 10 VDD
0 0 0 0 1 00 1 1 1 1 C B A
0 0 0 1 1 01 1 1 1 1 B C
0 0 1 0 1 11 1 0 0 0
A
D
0 0 1 1 1 10 1 0 0 1
0 1 0 0 1 D
0 1 0 1 1 F = A’+C’D’+B’D’
F
0 1 1 0 1
0 1 1 1 1 F’ = AD+ABC
1 0 0 0 1
A
F
1 0 0 1 0
1 0 1 0 1
D
1 0 1 1 0 B
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0 C
1 1 1 1 0

GND

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STICK DIAGRAMS
Complex Circuits
F = ((A+B+C)D)’
CD
VDD
A B C D F AB 00 01 11 10 VDD
0 0 0 0 1 00 1 1 0 1 A B C D
0 0 0 1 1 01 1 0 0 1 A
0 0 1 0 1 11 1 0 0 1
0 0 1 1 0 10 1 0 0 1
0 1 0 0 1 B D
0 1 0 1 0 F = D’+A’B’C’
0 1 1 0 1 F’ = BD + AD + CD F
0 1 1 1 0 C
= D(A+B+C)
1 0 0 0 1
F
1 0 0 1 0
1 0 1 0 1
D
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
A B C
1 1 1 1 0

GND
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STICK DIAGRAMS
CMOS XOR
VDD

VDD VDD

A
A B OUT B
F

GND
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THANK YOU!
Any Question?

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