49 views

Uploaded by Prasanna Wagh

save

- New Microsoft Word Document
- Algorithms for Marketing-Mix Optimization
- Computer Organization and Design 4th Edition Chapter 1 Slides
- Chapter 2_ Hardware Basics_ Inside the Box.pdf
- 7
- Paint
- Faa 0039
- Advanced computer architecture
- finalpdfc3pu
- GA-1000 User Manual 2
- Untitled
- Overview.pdf
- Deconstructing Cache Coherence With CRAG
- BN104 Lecture 1 Introduction.pptx
- Verilog Design and Fpga Prototype of a Nano Controller
- Tensor Flow
- ti_func
- Summary (Notes) for IT
- PL SQL Exercise4
- MCS-012 BLOCK 4
- Algebra Exam 2017
- 3computer Arch Outline
- Generating FPGA Accelerators for Chemical Similarity Assessment.pdf
- Computer Bus
- SOC Architecture design
- Math Camp Review Exam
- Wilson
- Module 3
- Embedded Security System in Automated Teller Machine
- venn
- Sample
- Gift_Magi
- Rob Miles CSharp Yellow Book 2010
- Networks & Distributed Computing

You are on page 1of 45

**Eli Gafni UCLA
**

Porquerolles, 5/6/03

Outline

Tasks Model of Computations as Tasks Solving a task in a Model SWMR Task Characterization of Wait-Free Solvability Resiliency and Strong Primitives (BG Sim) Uniform Tasks and Protocols Methodology Characterization Open Problems

**Distinguish Models by the Set of Tasks They Solve
**

Task:

± An input output relation from input i-tuples to sets of output i-tuples, i=1,«,n

Ti : Vi 2Vi

± (p1) {(p1)} ± (p2) {(p2)} ± (p1,p2) {(p1,p1), (p2,p2)}

Models of Computation

Tasks viewed as Rewrite system:

± (p1) {(p1)} ± (p2) {(p2)} ± (p1,p2) {((p1),(p1,p2)),((p1,p2),(p1,p2)), ((p1,p2),(p2))} ± 2 processors SWMR one-shot

(p2. (p1.p1).p2)} Solution p1: (p1) (p1).p2) {(p1. (p1.p2) (p2) (p1) .p2) p2: (p2) (p2).Can one-shot SWMR ³solve´ relaxed concensus? (p1) {(p1)} (p2) {(p2)} (p1.p1).(p2.

(p1.(p2))} p2 p2 .p2)).p2)).p2) {((p1).p2). ((p1.(p1.p2).((p1.Map of SWMR to relaxed cons Solution: ± (p1) {(p1)} p1 p2 ± (p2) {(p2)} p1 p2 p1 p1 ± (p1.

p2) p1:(p1. the cons output complex is disconnected: p1:(p1) p2:(p1) p1:(p2) p2:(p2) .Can One-Shot SWMR solve cons? p1:(p1) p1 p2:(p1.p2) map to there will be a p1-p2 edge The one-shot protocol complex is CONNECTED.p2) p2:(p2) p2 No matter what will (p1.

The Multi-Shot Protocol Complex Multi-shot can solve any task whose output is connected .

any number of each kind Two distinguished domino sides If able to tile any k-shot SWMR = solution= iff connectivity between the distinguished domino sides.Tiling View of Solving a Task The output dictates ³domino´ tiles. .

Q subset Sj (the last to write among a set of processors will read all of them. .«.pn-1} could this combination of sets arise as a result of writing and scanning the memory? ± pi in Si ± pi in Sj or pj in Si ± For all Q subset of P exists pj in Q.What is the Task spec of one-shot SWMR? For each pi given a set Si subset of P={p0.

each member return P. Project Sn off all Si and recurse.SWMR Spec A nonempty set Sn. Immediate Snapshots: ± pi in Si ± pi in Sj or pj in Si ± pi in Sj then Si subseteq Sj SWMR iff fat immediate snapshots .

n-1 At each stage input of pi=pi.1.N-shot SWMR solves ISn Stages 0. .«. If at stage k |Si|=n-k then pi returns Si.

The Protocol Complex of oneshot IS3 .

The Protocol Complex of twoshot IS3 To solve a task T3 you need to tile some ISk .

Approximate black-red edges with black-red path. .If able to tile any subdivided simplex. able to tile ISk Isk creates fine chromatic greed.

2 set-cons is not solvable by 3 processors Each processor outputs a participating processor id. . Sperner Lemma: Every tiling of a triangle must include a tile of the 3 distinct colors. The union the ids in a tuple leq 2.

Each output tuple contains one or two 0¶s.2 test-and-set is not solvable by 3 processors Each processor outputs 0 or 1. Reduction to 2 set-consensus .

return 1. otherwise.4} All values in a tuple are distinct Participating set size 1 returns 1.3. Reduction to 2 tst: if output 1 or 2. size 2 does not return 4.2. return 0.3 processors uniform renaming impossible with 4 slots Each processor output a value in {1. .

r w.r p2 p3 Each instruction goes thru agreement protocol: w. 2 proceed. 2 Simulators wait free.r. . If both see each other lower id win. write what you read. wait until other processor write what read or did not w at all. = valid bwhavior of 1 resilient. otherwise the one who did not see the other. Agreement blocks at most 1 code.Can 3 processors 2-resilient solve cons? p1 w.r w.

When is a task solvable by 3 processors 2 resilient? Output connected The link of a vertex connected The output of blue-red going alone .

The output of red going alone .When is a task solvable by 3 processors with test-and-set? Output connected The link of a vertex not necessarily connected The output of red-black alone when red ³wins´.

MP model = iterate the task! Communication closed layers .What about Message-Passing MP=SWMR-SM provided majority resilient. Below majority MP disconnects. MP task=each processor outputs a set of at least a majority.

it returns the set of processors it heard about and finished simulating its part of SWMR stage 1. At the next round majority will have a majority in common When a processor hears from majority that has heard about it. .Iterated MP=Iterated SM Key observation: Since each hears from majority. Etc. then majority hears from one.

Round by Round Failure Detector At each round a processor pi waits either to hear from processor pj. or on a failure detector module that announces pj to be faulty. . Can investigate what are the minimal requirements on a FD to be able to solve a task Tn (does there exist a minimum?).

in Asynch it was slow and now comes back I. pj completely crashed in the next round .Synchrony vs Asynchrony When thinking iterated the difference is that in Synch once pi does not hear from pj.e. Static vs Mobile failures Asynch = Synch with Mobile Omission failures .

Since 1-resilient asynch cannot solve cons. it takes at least k+1 round of synch Can be extended to crash failure thru reduction.Corollary: Synch with k (static) omission failures cannot be distinguished from 1-resilient asynch prior to round k+1 (expend 1 failure at a Synch round). .

Want a solution that does not depend on n! What is then the problem solved and how do you formally say ³no n in the solution´? .Uniform Protocols The solution to the immediate snapshot problem takes n as a parameter.

Example Task: Snapshot i P.1. 0 read 1.i Si P i.2} ! { 0 . 2 } 0 write 0. 2 read 0-1-2 . 0 read 0. 2 write 2. 1 write 1.1. 1 read 0-1-2. j P. 0 read 2.2: S S S 0 1 2 ! {0.(Si Sj)(Sj Si) The following is not a snapshot of 3 processors 0.1 } ! { 0 .

C1. Read Cj.« until encounter the first bk=0.bi To 1.«..Uniform Solution to the Snapshot Task Write i to Ci Scan C0. .. j=0..Cn-1 successively until return same sets in two successive scans. When writing Ci set b0. Complexity O(n2) ³Reduce Complexity´.With each Ci there is a MWMR associated bit bi initially 0.

else ± Oi := Scan C0. Consequently.«.Cn-1 If |Oi|<(n/2)+1 return i. Complexity O(n log n) .Cn-1 ± Return Oi Continue inductively (0.(n/2.n-1) Large did not finish first scan before small scan (otherwise small Scan is strictly after large scan).«.(n/2)).Non-Uniform Snapshot Protocol [HR93] Write i Oi := Scan C0. second large scan Is strictly after small write.

n algorithm and still recover in case some from n+1. Want to operate the 1.n to participate.2n but expect only 1. .Uniformization of the O(nlogn) Snapshot protocol Suppose I have 2n processor 1.n arrive.

2n registered: No: processor i departs Yes: Joins the protocol 1.n.n protocol. and checks whether any of the n+1.2n with Si as input ± Processor n+1. .Uniformization of the O(nlogn) Snapshot protocol (cont¶) Idea: ± Processor 1. ± When i<n+1 terminates.2n takes its input to be its id union the largest Si it observe posted in 1.n executes the 1. it posts Si.

When i<n+1 terminates.2n takes as ³input¶¶ all the Sj¶s it observe posted. . and checks whether any of the n+1. All register upon arrival.2n registered: ± No: processor i departs ± Yes: Joins the protocol 1. Processor first drops tokens on behalf of the smallest Sj in its input.2n with all the largest Sj smaller than Si posted Processor in n+1.n executes the 1. it posts Si.Uniformization of the Immediate Snapshot (IS) Protocol Processor 1.n protocol.

Complexity O(k3) but know better O(k2) . it stops dropping token i at line k ± Processor i when dropping token i if processor j at line k signaled it is dropping i.Uniformization of the Immediate Snapshot (IS) Protocol (Cont¶d) After that it drops tokens on its behalf Processor i may RETURN at line k while processor j may drop token i further down later: ± Processor j at line k with token i signals (raises flag) it intend to drop token I to k-1 ± It then reads level k again If number of distinct token in k <k it drops token i to k-1 Else. drops i to k-1 no matter if k distinct tokens at level k.

«. Tk+1. where Tk is over processors 0.«. T1.«.Tk.k and Tk+1 extends Tk (Tk+1 over participating set without k+1 is Tk. and every k solution extends to k+1) Solution to Tk+1 extends solution to Tk .Definition of a Uniform Task and a Uniform Protocol Sequence of tasks T0.

.Methodology Given a Uniform task T.BC-T2i+1.BC-T2i. then processor i has to halt with that output Solve . solve Backward-Compatible Tn (BC-Tn): ± Processors in BC-Tn each wake up with a partial solution to Tn (all factions of the same solution) ± Solve Tn such that if all processors wake up with solution to processor i.«.« Conjecture: Since the simplex convergence is BC solvable any BC solvable task has same complexity as the original task.

« ± If |Si| is large then j spent little complexity in the IS ± If |Si| is small then few processors participate later in the inductive IS together with it. 2|Si|-2. Take IS. uniformize IS . if highest id in Si output 2|Si| -1 ± All processors j of same cardinality |Sj| continue inductively on slots 2|Si|-1.2k-1.Application: 2) O(k Renaming Tk : k processors rename into range 1. Complexity O(n2).

Solvable Uniform Task .No Uniform Solution SDS1(S2) a b c d .

No Uniform Solution (cont¶ed) SDS2(S2) a b c d c b a b c d .Solvable Uniform Task .

only that the face p0. .b.Solvable Uniform Task .p1 maps snakewise to a.« Tn is obviously solvable by taking enough steps to produce SDSn(s3).d.c.pn-1.pn output SDSn(s3).c.No Uniform Solution (cont¶ed) For Tn n-even processors p0.p1.

by considering only the LAST i iterations. . say.No Uniform Solution (cont¶ed) For the Uniform version of Tn (downward compatible) pi chooses a vertex in SDSn(s3) but maps it to a vertex in SDSi(s3). c and d. Not solvable uniformly. since pn-1 and pn do not ³know´ which actual vertices p0 and p1³meant´ by outputting.Solvable Uniform Task . respectively.

Characterization of Uniform Solvability HS: A task on n+1 processor is solvable iff there exist a map from the output to an ndim subdivided simplex. Uniform Solvability: The map to the n+1dim subdivided simplex extends the map to the n-dim subdivided simplex .

Idea of Proof Of the Characterization IIS model that gives rise to a protocol complex which is a subdivided simplx Show equivalence of IIS to standard asynchronous model by showing UNIFORM emulations between the standard and the IIS model. .

Adaptive Algorithms = Uniform Algorithms for Symmetric problems (e.Connection to Adaptive Algorithms Adaptive Algorithms: Distributed Algorithms whose Step Complexity is a Function of the Number of Participating Processors Rather than n.g. Snapshots) .

Open Problem(S) Extend to infinite arrival guaranteeing ± Non-Blocking ± Waitfreeness How do you formulate such a problem as a task? .

- New Microsoft Word DocumentUploaded byNeela Murali
- Algorithms for Marketing-Mix OptimizationUploaded byRamona Georgiana
- Computer Organization and Design 4th Edition Chapter 1 SlidesUploaded byMark Perkins
- Chapter 2_ Hardware Basics_ Inside the Box.pdfUploaded bySasurika Uchiha
- 7Uploaded byJose C. Garcia R
- PaintUploaded byvijay2101
- Faa 0039Uploaded bySuzaini Supingat
- Advanced computer architectureUploaded byjulianraja20
- finalpdfc3puUploaded byMarko Karlovic
- GA-1000 User Manual 2Uploaded byJason Wu
- UntitledUploaded byDanubio Alves
- Overview.pdfUploaded byHerbet Filipe
- Deconstructing Cache Coherence With CRAGUploaded byIvan Rasmussen
- BN104 Lecture 1 Introduction.pptxUploaded bySubodh Poudyal
- Verilog Design and Fpga Prototype of a Nano ControllerUploaded byगौरव सैनी
- Tensor FlowUploaded byhanifalisohag
- ti_funcUploaded byurcoad
- Summary (Notes) for ITUploaded byKok Yong Shun
- PL SQL Exercise4Uploaded byNishant Andhale
- MCS-012 BLOCK 4Uploaded byAbhishek Veerkar
- Algebra Exam 2017Uploaded byAnonymous PV7Vpc
- 3computer Arch OutlineUploaded bychurch123
- Generating FPGA Accelerators for Chemical Similarity Assessment.pdfUploaded byBoppidiSrikanth
- Computer BusUploaded byQuincy Joy Bartolome Pasahol
- SOC Architecture designUploaded byShravaniKashyap
- Math Camp Review ExamUploaded bycan
- WilsonUploaded byVeera Venkat Raja
- Module 3Uploaded byVarghese Thomas E
- Embedded Security System in Automated Teller MachineUploaded bySam Raj
- vennUploaded byNaseha Arshad