Simplified FPGA design implementation flow


ASIC Design Flow


Design methods
1. 2. 3. 4. 5. Behavioral synthesis RTL synthesis Logic Synthesis Structural-to-Layout synthesis Layout synthesis

 Behavioral synthesis allows design at higher levels of abstraction by automating the translation and optimization of a behavioral description.  Behavioral level is technologyindependent. Behavioral synthesis At the behavioral level. the operation of the system is captured without specifying the implementation. into an RTL implementation.  .1. including I/O actions and computational functionality. or high-level model.  This process starts with a high-level language description of a module's behavior.

. LAGER compiler.  A behavioral compiler must perform the following operations:     Decide and assign resources based on area and timing requirements Insert pipeline registers to achieve timing constraints.Behavioral synthesis The other inputs to the synthesis process are a target technology library. for the selected fabrication process. and a set of directives that will influence the resulting architecture.  Silicon compilers such as Cathedral series. Create microcode and/or control logic.  Several algorithmic optimizations are performed to reduce the complexity and then the description is analyzed to determine the essential operations and the dataflow dependencies between them.

Hardware describing languages (HDL)       Describe behavior not implementation Make model independent of technology Model complete systems Specification of sub-module functions Speed up simulation of large systems Standardized text format .

Design entry  Text:    Tool independent Good for describing algorithms Bad for getting an overview of a large design .

Add-on tools     Block diagrams to get overview of hierarchy Graphical description of final state machines (FSM)  Generates synthesizable HDL code Language sensitive editors Waveform display tools From Visual HDL. Summit design .

RTL Synthesis    RTL-synthesis programs take an RTL description and convert it to a set of registers and combinational logic. Sequential Vs parallel operations. . Register specification and allocation.2. Arithmetic and logic operations. RTL descriptions are captured using Hardware Description Language (HDL). HDL description includes     Control flow using if-then-else and case statements.   RTL compiler converts a HDL description into a set of registers and combinational logic. RTL synthesis tool: Synopsys VHDL Compiler.

case. if-then-else. Logic synthesis  HDL compilation (from VHDL or Verilog)   Registers: Logic: Where storage is required Boolean equations. etc.3.  Logic optimization     Logic minimization (similar to Karnaugh maps) Finds logic sharing between equations Maps into gates available in given technology Uses local optimization rules 3 logic gates 6 basic CMOS gates 3 basic CMOS gates .

Logic Optimization  Logic optimization programs take logic descriptions generated by RTL synthesis and optimize the logic network of the gates to meet both speed and area constraints. .  The register are then reunited with optimized logic.  The physical layout then may be implemented using available automatic techniques.

Logic Optimization contd optimization Compile Net-list generation (Technology mapping) Extract Logic equation Net list input input .

the logic optimization systems divide the problem into two stages:   A technology independent phase in which the logic is optimized according to algebraic and/or Boolean techniques. A technology mapping phase. that translates the technology independent description to specific library cells.  Generally.Logic Optimization contd . Network organization Two-level minimization Algebraic decomposition of two-level logic expression into multi-level logic expression (weak division) Iterative improvement  A typical logic optimization flow:     .

Software for Logic Synthesis .Software tools for logic synthesis  Software tools for logic synthesis targeting ASICs     Design Compiler by Synopsys Encounter RTL Compiler by Cadence Design Systems TalusDesign by Magma Design Automation BooleDozer: Logic synthesis tool by IBM (internal IBM EDA tool)  Software tools for logic synthesis targeting FPGAs          Encounter RTL Compiler by Cadence Design Systems LeonardoSpectrum and Precision (RTL / Physical) by Mentor Graphics Synplify (PRO / Premier) by Synplicity BlastFPGA by Magma Design Automation Quartus II integrated Synthesis by Altera XST (delivered within ISE) by Xilinx DesignCompiler Ultra and IC Compiler by Synopsys IspLever by Lattice Semiconductor GeneXproTools .

 There are two mainly used automated algorithms for placement.  Includes two phases  Placement  Routing  Placement:  Placement is the task of placing modules adjacent to each other to minimize area and delay.4. . Structural-to-Layout Synthesis  Automatically converts the net-list of gates and registers to physical layout.

Structural-to-Layout Synthesis  contd Min-cut Algorithm:  It takes the top-level modules to be placed and finds two equal area-groupings of sub-blocks with the minimum number of signal interconnections.  Modules are initially allowed to move randomly and the temperature of the layout is evaluated by applying some measures such as routing area and timing.  These two blocks are then placed in the top and bottom half of a conceptual final layout.4. the routing and/or timing improves.  Another popular technique is similar to thermal annealing.  This algorithm is very fast and gives good performance. splitting the conceptual layout into quarters and so on until the leaf cells are reached.  As the layout cools.  Same process is repeated for these two halves. .

Different types of routers are: Channel routers are used to route rectangular channels.4. . Switchbox routers are used to route more complex channels. Maze routers are used to route any configuration but have comparatively long running times. Structural-to-Layout Synthesis contd  Routing: A router connects the modules with wires.

while others create symbolic layouts that may be compacted to suit a particular technology. data paths and multipliers may be synthesized by software generators. The combination of symbolic layout. a powerful language and a good CAD tools may create powerful layout generators with minimum effort. PLAs registers. Some systems create actual mask layout tuned to a particular process. . Layout Synthesis     The layout of regular structures such as RAMs. These programs take a number of parameters as input and automatically create a custom physical layout.5. ROMs.

2. 5. HDL Design Schematic Design Layout Design Floor-planning Chip Composition . 4.Design capture tools 1. 3.

ELLA. Pascal. HDL Design  The behavior and/or structure of a system may be captured in HDL such as VHDL. Verilog and modified high level languages such as C.1. .

.2. Layout Design    Layout can be captured via code or interactive graphic editors. Design rule checking (DRC) programs allows interactive checking of DRC errors and circuitconnectivity issues. A good color editor is strongly required if substantial layout editing is to be performed.

Schematic Design   Schematic editor provide a means to draw and connect components. selecting and deleting parts. . The schematic editors provides     Creating.3. connections. Selecting an electrical node and interrogating it for state. zooming or other means. capacitance etc. Running an attached simulator. Changing the graphic view by panning.

  . Floorplanning   Floorplanning is the exercise of arranging blocks of layout within a chip to minimize area or maximize speed. The editors also show connectivity information between modules in the form of rat s-nest wiring diagram. Floorplan editors provide graphical feedback about the size and placement of modules without showing internal layout details. where the connected ports of modules are connected by straight lines. The floorplanning may be done automatically but many times a much better job can be done manually.4.




Simulation      Circuit-level Simulation Timing Simulation Logic-level Simulation Switch-level simulation Mixed mode simulation .Design Verification Tools 1.

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