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# EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 8: 8.

4

Counters

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**Agenda for Today
**

Counters

± Definition ± Types ± Characteristics

Count Clock Counter

** Asynchronous Counters Synchronous Counters MSI Counters
**

± Especially the 74LS163

optional inputs

S1 Sm

S2 S3 S4 S5

Counters in VHDL Other Counter Types

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Counters

A counter is a circuit that produces a numeric count each time an input clock pulse makes an active transition

Clock

Counter

Count

Load an initial value, reset to starting count, etc.

May also enable count, select direction, etc.

optional inputs

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counters are a special case of a finite state machine Output is usually the state value. Moore machine RESET EN EN EN EN EN EN S1 S2 EN S3 Sm EN EN EN EN EN S4 S5 EN 4 . a counter is any sequential circuit whose state diagram is a single cycle ± in other words.Counter From another viewpoint.

Counters Counters differ by a number of basic characteristics. including: Characteristic Description Modulus Coding Direction Resetable Loadable Length of sequence Count sequence Up or down Reset to zero Load a specific value 5 .

delays watches.Counters Applications include: ± ± ± ± ± ± ± ± ± system clock timer. clocks. alarms counting events memory addressing frequency division sequence control cycle control protocols Present State A B 0 0 1 1 0 1 0 1 Next State A B 0 1 1 0 1 0 1 0 00 01 11 10 6 .

Synchronous ± Clocked 000 101 001 Ring Johnson ± Twisted ring Up/Down LFSR 010 011 7 100 .Counter Types Asynchronous ± Ripple Modulus ± Binary ± Decade ± etc.

Counters

Some examples of modulus and coding sequence for counters

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Counters

Modulus

± number of states in a counter¶s cycle

Given m states

± modulo-m counter or divide-by-m counter

** Power-of-2 counters use all states Non-power-of-2 counters have extra, unused states
**

S1 Sm S4 S5

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S2 S3

**Example 4-bit Counters
**

4-bit Binary / Hex / Mod-16 Counter

± 0000, 0001, 0010, « 1110, 1111, 0000, 0001, « all states used

** 4-bit BCD / Decade / Mod-10 Counter
**

± 0000, 0001, 0010, « 1000, 1001, 0000, 0001, « six unused states

** 4-bit Ring Counter
**

± 1000, 0100, 0010, 0001, 1000, 0100, « twelve unused states

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with the exception of the first. is taken from the output of the preceding one ± the count thus ripples along the counter's length due to the propagation delay associated with each stage of counting 11 .Counters Ripple counters ± asynchronous ± an n-state counter that is formed from n cascaded flip-flops ± the clock input to each of the individual flip-flops.

. . 12 .Asynchronous Ripple Counter Q0 Q1 Q2 Q3 Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 .

Ripple Counter Timing The ideal count sequence for the ripple counter yields the timing diagram below Q0 Q1 Q2 Q3 CLOCK Q0 Q1 Q2 Q3 13 .

Ripple Counter Timing But there is delay ( ( ) as shown below: CLK Q0 1( Q1 2( Q2 3( 0 1 2 3 4 14 .

Asynchronous Ripple Counter Q0 divide-by-2 Q1 divide-by-4 a T flip-flop is a flipnatural frequency divider « Q2 divide-by-8 Q3 divide-by-16 15 .

Synchronous Counters Asynchronous counters are easy to understand. but avoid their use ± slow. limited by propagation delays ± error prone Characteristics of synchronous counters ± use a common clock pulse to trigger all flip-flops simultaneously ± have a higher clock speed ± hardware is more complex but more reliable 16 .

4-Bit Counter LSB Synchronous counter serial enable logic MSB 17 .

4-Bit Counter LSB Synchronous counter parallel enable logic MSB 18 .

74x163 74x163 74x168. 74x92. ± 7470 ± 7474 ± 7479 ± ± ± ± ± and many others « D1 D2 Counters may also be built using MSI components 74x90. 74x197 we¶ll look at this one 19 . 74x161.MSI Counters Counters can be built from individual SSI Flip-Flops. 74x93 74x160. 74x162.g. 74x191 74x196. e. 74x169 74x190..

MSI Counter 4-bit synchronous counter ± edge-triggered ± synchronously presettable ± cascadable Typical Count Rate of 35 MHz µ160 and µ162. Mod-10 µ161 and µ163. Mod-16 20 .

MSI Counter 74LS163 4-bit synchronous counter 16-pin DIP 16- 21 .

MSI Counter 74LS163 characteristics ± ± ± ± edge-triggered synchronously presettable cascadable count modulo 16 (binary) 74x163 Synchronous Reset (Clear) input that overrides all other control inputs ± active only during the rising clock edge 22 .

MSI Counter 74LS163 logic symbols datasheet text 74x163 23 .

MSI Counter 74LS163 state diagram and logic equations 24 .

MSI Counter 74LS163 mode select table All signals must be high ( H ) to enable the count sequence to begin 25 .

MSI Counter 74x163 is a synchronous 4-bit binary counter RCO=1 when all count bits are 1 and ENT is asserted 26 .

MSI Counter The control inputs for the 74x163 have the following effects: clear load hold hold 27 .

three-state outputs 74696: 4-bit Decimal Counter/Register/Multiplexer with Asynchronous Reset. Three-State Outputs 74692: 4-bit Decimal Counter/Latch/Multiplexer with Synchronous Reset. Synchronous 74293: 4-bit Binary Counter (separate divide-by-2 and divide-by-8 sections) 74390: Dual 4-bit Decade Counter 74393: Dual 4-bit Binary Counter 74452: Dual Decade Counter. Synchronous. three-state outputs 74716: Programmable Decade Counter 74718: Programmable Binary Counter 28 . three-state outputs 74697: 4-bit Binary Counter/Register/Multiplexer with Asynchronous Reset. three-state outputs 74699: 4-bit Binary Counter/Register/Multiplexer with Synchronous Reset. 15 mA Constant Current 74144: Decade Counter/Latch/Decoder/7-segment Driver. Binary Up/Down Counter. Preset Input 74461: 8-bit Presettable Binary Counter with three-state outputs 74490: Dual Decade Counter 74491: 10-bit Binary Up/Down Counter with Limited Preset and three-state logic outputs 74560: 4-bit Decade Counter with three-state outputs 74561: 4-bit Binary Counter with three-state outputs 74568: Decade Up/Down Counter with three-state outputs 74569: Binary Up/Down Counter with three-state outputs 74590: 8-Bit Binary Counter with Output Registers and three-state outputs 74592: 8-Bit Binary Counter with Input Registers 74593: 8-Bit Binary Counter with Input Registers and three-state outputs 74668: Synchronous 4-bit Decade Up/Down Counter 74669: Synchronous 4-bit Binary Up/Down Counter 74690: 4-bit Decimal Counter/Latch/Multiplexer with Asynchronous Reset. Three-State Outputs 74693: 4-bit Binary Counter/Latch/Multiplexer with Synchronous Reset. Preset Input 74455: Dual Binary Up/Down Counter. Synchronous 74454: Dual Decade Up/Down Counter.MSI Counters 7458: Dual 4-bit Decade Counter 7459: Dual 4-bit Binary Counter 7468: Dual 4 Bit Decade or Binary Counters 7469: Dual 4 Bit Decade or Binary Counters 7490: Decade Counter (separate Divide-by-2 and Divide-by-5 sections) 7492: Divide-by-12 Counter (separate Divide-by-2 and Divide-by-6 sections) 7493: 4-bit Binary Counter (separate Divide-by-2 and Divide-by-8 sections) 74142: Decade Counter/Latch/Decoder/Nixie Tube Driver 74143: Decade Counter/Latch/Decoder/7-segment Driver. Three-State Outputs 74694: 4-bit Decimal Counter/Latch/Multiplexer with Synchronous and Asynchronous Resets. Synchronous 74453: Dual Binary Counter. Synchronous. 15V open collector outputs 74160: Synchronous 4-bit Decade Counter with Asynchronous Clear 74161: Synchronous 4-bit Binary Counter with Asynchronous Clear 74162: Synchronous 4-bit Decade Counter with Synchronous Clear 74163: Synchronous 4-bit Binary Counter with Synchronous Clear 74168: Synchronous 4-Bit Up/Down Decade Counter 74169: Synchronous 4-Bit Up/Down Binary Counter 74176: Presettable Decade (Bi-Quinary) Counter/Latch 74177: Presettable Binary Counter/Latch 74190: Synchronous Up/Down Decade Counter 74191: Synchronous Up/Down Binary Counter 74192: Synchronous Up/Down Decade Counter with Clear 74193: Synchronous Up/Down Binary Counter with Clear 74196: Presettable Decade Counter/Latch 74197: Presettable Binary Counter/Latch 74290: Decade Counter (separate divide-by-2 and divide-by-5 sections) 74291: 4-bit Universal Shift register. Three-State Outputs 74691: 4-bit Binary Counter/Latch/Multiplexer with Asynchronous Reset. three-state outputs 74695: 4-bit Binary Counter/Latch/Multiplexer with Synchronous and Asynchronous Resets. three-state outputs 74698: 4-bit Decimal Counter/Register/Multiplexer with Synchronous Reset.

architecture V74x163_arch of V74x163 is signal IQ: UNSIGNED (3 downto 0).all. CLR_L. 29 . entity V74x163 is port ( CLK. IQ) begin if (CLK'event and CLK='1') then if CLR_L='0' then IQ <= (others => '0').std_logic_1164. ENT: in STD_LOGIC.Counters in VHDL VHDL code for a 74x163 like 4-bit binary counter library IEEE. use IEEE. elsif LD_L='0' then IQ <= D. Q <= IQ. elsif (ENT and ENP)='1' then IQ <= IQ + 1. end if. ENT. end if. end if.all. Q: out UNSIGNED (3 downto 0). LD_L. end V74x163_arch. use IEEE. if (IQ=15) and (ENT='1') then RCO <= '1'. ENP. RCO: out STD_LOGIC ).std_logic_arith. D: in UNSIGNED (3 downto 0). else RCO <= '0'. end V74x163. end process. begin process (CLK.

RCO: out STD_LOGIC ). use IEEE.std_logic_1164. Q: out UNSIGNED (3 downto 0). CLR_L. IQ) begin if CLK'event and CLK='1' then if CLR_L='0' then IQ <= (others => '0'). begin process (CLK.'1'). end process. else RCO <= '0'. ENT: in STD_LOGIC. architecture V74xs3_arch of V74xs3 is signal IQ: UNSIGNED (3 downto 0). LD_L. end V74xs3_arch. ENP. Q <= IQ. D: in UNSIGNED (3 downto 0). end if. elsif (ENT and ENP)='1' then IQ <= IQ + 1. elsif LD_L='0' then IQ <= D.all. end if.all.std_logic_arith. elsif (ENT and ENP)='1' and (IQ=12) then IQ <= ('0'.'0'. entity V74xs3 is port ( CLK. 30 . use IEEE. if (IQ=12) and (ENT='1') then RCO <= '1'. end if. end V74xs3.Counters in VHDL VHDL code for counting in the excess-3 sequence library IEEE. ENT.'1'.

QN: out STD_LOGIC ). QN <= not D. end Vdffqqn. Q. 31 .Counters in VHDL Component of the previous code library IEEE. end process. use IEEE. architecture Vdffqqn_arch of Vdffqqn is begin process(CLK) begin if (CLK'event and CLK='1') then Q <= D.all.std_logic_1164. end Vdffqqn_arch. end if. D: in STD_LOGIC. entity Vdffqqn is port( CLK.

std_logic_1164. end generate. ENT: in STD_LOGIC. CNTEN: in STD_LOGIC. -. CNTENP.serial count-enable into the first stage g1: for i in 0 to 7 generate -. D(i). Q: out STD_LOGIC_VECTOR (7 downto 0). CLR_L. end V74x163s.generate the eight syncsercell stages U1: syncsercell port map ( CLK.RCO is equivalent to final count-enable output end V74x163s_arch.create common load and clear controls NOCLRORLD <= LD_L and CLR_L. NOCLRORLD: STD_LOGIC. -.all. RCO: out STD_LOGIC ). Q(i)). D. -. LDNOCLR. ENP. LD_L.Counters in VHDL VHDL program for 8-bit 74x163 like synchronous serial counter library IEEE. ENP.common signals signal SCNTEN: STD_LOGIC_VECTOR (8 downto 0). LDNOCLR. D: in STD_LOGIC_VECTOR (7 downto 0). RCO <= SCNTEN(8). SCNTEN(i). -. -. SCNTEN(0) <= ENT. SCNTEN(i+1). signal LDNOCLR. Q: out STD_LOGIC ). NOCLRORLD.serial count-enable inputs begin LDNOCLR <= (not LD_L) and CLR_L. 32 . use IEEE. end component. entity V74x163s is port( CLK. architecture V74x163s_arch of V74x163s is component syncsercell port( CLK. NOCLRORLD. CNTENO.

74x163 Internal Logic Diagram XOR gates embody the ³T´ function Mux-like structure for loading One of the four bit ³cells´ 33 .

74x163 like counter 34 .Counters in VHDL 1-bit cell of a synchronous serial.

end syncsercell. DIN. 74x163 like counter library IEEE. NOCLRORLD. Q_L: STD_LOGIC. CDAT <= NOCLRORLD and ((CNTENP and CNTEN) xor not Q_L). end component. Q. end syncsercell_arch. Q_L). QN: out STD_LOGIC ). CNTENP.all. entity syncsercell is port( CLK. signal LDAT. Q.Counters in VHDL 1-bit cell of a synchronous serial. 35 . CDAT. LDNOCLR. DIN. architecture syncsercell_arch of syncsercell is component Vdffqqn port( CLK. CNTENO. CNTENO <= (not Q_L) and CNTEN. U1: Vdffqqn port map (CLK. CNTEN: in STD_LOGIC. D: in STD_LOGIC. Q: out STD_LOGIC ). begin LDAT <= LDNOCLR and D.std_logic_1164. use IEEE. DIN <= LDAT or CDAT. D.

Counter Operation Free-running z16 Count if ENP and ENT both asserted Load if LD is asserted (overrides counting) Clear if CLR is asserted (overrides loading and counting) All operations take place on rising CLK edge RCO is asserted if ENT is asserted and Count = 15 makes it free-running free- 36 .

Free-Running 4-Bit ¶163 Counter ³divide-by-16´ counter RCO is asserted if ENT is asserted and Count = 15 37 .

12. 11. « ³divide-by-11´ counter 38 . 7. 10.Modified Counting Sequence DCBA Load 0101 (5) after Count = 15 5. 6. 5. 8. 15. 14. 13. 9. 6.

2. 9. 7.Another Way saves gate inputs Clear after Count = 1010 (10) 0. 1. « ³modulo-11´ or ³divide-by-11´ counter 39 . 8. 1. 4. 2. 6. 5. 3. 3. 0. 10.

Counting from 3 to 12 40 .

Cascading Counters RCO (ripple carry out) is asserted in state 15. if ENT is asserted 41 .

Decoding Binary-Counter States 42 .

Decoder Waveforms Glitches may or may not be a concern 43 .

Glitch-Free Outputs Registered outputs delayed by one clock cycle 44 .

Modulo-10 Counters From the 74LS163 ³family´ ± the 74LS160 ± 74LS160 in free-running mode ± Duty cycle of QC and QD is not 50% 45 .

13. 14. 46 . 12. or 15. it will return to its normal sequence within two clock pulses. but will not count beyond 9. 11.Modulo-10 Counters 74LS160 state diagram The 74LS160 (and 74LS162) can be preset to any state. If preset to state 10.

the specified state will shift to the next device at a rate of 1 shift per clock. then only one device may be HIGH at one time. or input.Ring Counter A ring counter is a loop of flip-flops interconnected in such a manner that only one of the devices may be in a specified state at one time If the specified state is HIGH. signal is received. pulse. As the clock. 47 . or input.

Ring Counter A typical four-stage ring counter Composed of R-S FFs. of the nearest FF and to the S. ± J-K FFs may be used as well Output of each AND gate is input to the R. or set side. of the next FF Q output of each FF is applied to the B input of the AND gate that is connected to its own R input 48 . or reset side.

and parallel-parallel data register transfers 49 . serialparallel. shift right. shift left.Another MSI Device 74LS194 is a 4-Bit Bidirectional Universal Shift Register may be used in serial-serial. parallel-serial.

Another MSI Device The µ194 has the circuitry needed to count 50 .

Shift-Register Counters Ring counter 51 .

Johnson Counter ³Twisted ring´ counter 52 .

1 states before repeating Same circuits used in CRC error checking in Ethernet networks.LFSR Counters Pseudo-random number generator 2n . 53 . etc.

LFSR Counters Feedback equations for all values of n 54 .

or 10102 An ordinary four-stage counter can be easily modified to a decade counter by adding a NAND gate as shown below Notice that FF2 and FF4 provide the inputs to the NAND gate The NAND gate output is connected to the CLR input of each of the FFs 55 .Decade Counters A decade counter is a binary counter that is designed to count to 1010.

Counter Applications Digital Clock 56 .

Up/Down Counters A 3-bit binary up/down counter QA Clock Counter QB QC Count UP / DOWN 57 .

Up/Down Counters This circuit is a 3-bit UP/DOWN synchronous counter using JK flip-flops configured to operate as toggle or T-type flip-flops giving a count of zero (000) to seven (111) and back to zero again. either UP or DOWN and the timing diagram gives an example of the counters operation as this UP/DOWN input changes state. 58 . An additional input determines the direction of the count.

Up/Down Counters The 74LS169 is a fully synchronous 4-stage up/down counter Includes: ± a preset capability for programmable operation ± carry lookahead for easy cascading ± a U/ D input to control the direction of counting 59 .

Up/Down Counters The SN74LS169 operates in a Modulo-16 binary sequence 60 .

Up/Down Counters 74LS169 logic circuit diagram 61 .

Counter Applications 3-Bit Gray Code Counter 62 .

when others => Q <= ³000´. end if. end entity StateCounter.std_logic_1164. end architecture CounterBehavior.all. when ³101´ => Q <= ³001´. when ³110´ => Q <= ³100´. Q: buffer std_logic_vector(0 to 2) ). end case. when ³001´ => Q <= ³000´. when ³010´ => Q <= ³110´. end process.Counter Applications 3-Bit Gray Code Counter in VHDL library ieee. when ³100´ => Q <= ³101´. use ieee. architecture CounterBehavior of StateCounter is begin process (Clock) begin if Clock = µ1¶ and Clock¶event then case Q is when ³000´ => Q <= ³010´. entity StateCounter is port(clock: in std_logic. 63 .

Next Time Midterm returned Start MIPs design Counter design using FSM approach 64 .