Introduction to CMOS VLSI Design

CMOS Transistor Theory

Outline
Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models

MOS devices

CMOS VLSI Design

Slide 2

Introduction
So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current ± Depends on terminal voltages ± Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance ± I = C ((V/(t) -> (t = (C/I) (V ± Capacitance and current determine speed Also explore what a ³degraded level´ really means

MOS devices

CMOS VLSI Design

Slide 3

MOS Capacitor
Gate and body form MOS capacitor Operating modes ± Accumulation ± Depletion ± Inversion
Vg < 0 + (a) 0 < Vg < Vt + polysilicon gate silicon dioxide insulator p-type body

depletion region

(b)

Vg > Vt + inversion region depletion region

(c)

MOS devices

CMOS VLSI Design

Slide 4

Terminal Voltages
Mode of operation depends on Vg, Vd, Vs ± Vgs = Vg ± Vs s ± Vgd = Vg ± Vd s ± Vds = Vd ± Vs = Vgs - Vgd Source and drain are symmetric diffusion terminals ± By convention, source is terminal at lower voltage ± Hence Vds u 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation ± Cutoff ± Linear ± Saturation
MOS devices CMOS VLSI Design

s

Slide 5

nMOS Cutoff
No channel Ids = 0
Vgs = 0

+ -

g

s

+ d n+

Vgd

n+ p-type body b

MOS devices

CMOS VLSI Design

Slide 6

nMOS Linear
d

-

s

d n -t e od Vds

n

s

n

s

d n -t e od

Ids
 

MOS devices

CMOS VLSI Design

 

 

 

V

s

Vt

V

V

 

 

 

Channel forms Current flows from d to s V - from s to d ±e Ids increases with Vds Similar to linear resistor

s

Vt

V

V

s

d

Vt

Vds

V s-Vt

Slide 7

nMOS Saturation
Channel pinches off Ids independent of Vds We say current saturates Similar to current source
Vgs > Vt

+ -

g

s

+ -

Vgd < Vt

d Ids Vds > Vgs-V t

n+ p-type body b

n+

MOS devices

CMOS VLSI Design

Slide 8

I-V Characteristics
In Linear region, Ids depends on ± How much charge is in the channel? ± How fast is the charge moving?

MOS devices

CMOS VLSI Design

Slide 9

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion ± Gate ± oxide ± channel Qchannel =

gate
polysilicon gate W tox n L p-t pe od n SiO2 gate oxide (good insulator, Iox = 3.9)
g

source
s

gs

g

gd

n

-

channel
ds

-

drain n
d

p-t pe od

MOS devices

CMOS VLSI Design

Slide 10

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion ± Gate ± oxide ± channel Qchannel = CV C=
gate Vg
W tox n L p-t pe od n SiO2 gate oxide (good insulator, Iox = 3.9)

polysilicon gate

Cg Vgd drain source Vgs Vs Vd channel n n Vds p-t pe od

MOS devices

CMOS VLSI Design

Slide 11

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion ± Gate ± oxide ± channel Qchannel = CV Cox = Iox / tox C = Cg = IoxWL/tox = CoxWL V=
t
¢¡

W
£

t

x

L -t

(

SiO2 t xi i s l t r, Iox = 3.9)

-t

MOS devices

CMOS VLSI Design

¢

V

s

Slide 12

¢

c

¡

¡

polysilicon gate

s rc V Vs -

s

¡

V

V l

-

r i V

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion ± Gate ± oxide ± channel Qchannel = CV Cox = Iox / tox C = Cg = IoxWL/tox = CoxWL V = Vgc ± Vt = (Vgs ± Vds/2) ± Vt
polysilicon gate W
¤

g t Vg s rc Vgs Vs c (g SiO2 g t xid d i s l t r, Iox = 3.9)
g

t

Vgd dr i Vd l d

x

L -t d

Vds

-t

MOS devices

CMOS VLSI Design

Slide 13

Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between source and drain v=

MOS devices

CMOS VLSI Design

Slide 14

Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between source and drain v = QE Q called mobility E=

MOS devices

CMOS VLSI Design

Slide 15

Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between source and drain v = QE Q called mobility E = Vds/L Time for carrier to cross channel: ± t=

MOS devices

CMOS VLSI Design

Slide 16

Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between source and drain v = QE Q called mobility E = Vds/L Time for carrier to cross channel: ± t=L/v

MOS devices

CMOS VLSI Design

Slide 17

nMOS Linear I-V
Now we know ± How much charge Qchannel is in the channel ± How much time t each carrier takes to cross

I ds !

MOS devices

CMOS VLSI Design

Slide 18

nMOS Linear I-V
Now we know ± How much charge Qchannel is in the channel ± How much time t each carrier takes to cross

Qchannel I ds ! t !

MOS devices

CMOS VLSI Design

Slide 19

nMOS Linear I-V
Now we know ± How much charge Qchannel is in the channel ± How much time t each carrier takes to cross

I ds !

channel

t ¸V ¹ ds º
F = W
ox

¨V  V  Vds © gs t 2 ª ¨V  V  Vds ¸V ! F © gs t 2 ¹ ds ª º W ! QCox L
MOS devices

CMOS VLSI Design

Slide 20

nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain ± When Vds > Vdsat = Vgs ± Vt Now drain voltage no longer increases current

I ds !

MOS devices

CMOS VLSI Design

Slide 21

nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain ± When Vds > Vdsat = Vgs ± Vt Now drain voltage no longer increases current

¨ V  V  Vdsat I ds ! F © gs t 2 ª

¸V ¹ dsat º

MOS devices

CMOS VLSI Design

Slide 22

nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain ± When Vds > Vdsat = Vgs ± Vt Now drain voltage no longer increases current

I ds ! F ¨ © ª F ! 2

gs 

t 

dsat

¸ 2¹ º

dsat

gs 

t

2

MOS devices

CMOS VLSI Design

Slide 23

nMOS I-V Summary
Shockley 1st order transistor models

® ± 0 ± ±¨ Vds I ds ! ¯ F ©Vgs  Vt  2 ª ± 2 ± F Vgs  Vt ± ° 2
MOS devices

Vgs

Vt

cutoff linear saturation

¸V V V ¹ ds ds dsat º
Vds " Vdsat

CMOS VLSI Design

Slide 24

Example
Example: a 0.6 Qm process from AMI semiconductor ± tox = 100 Å ± Q = 350 cm2/V*s 2.5 V =5 ± Vt = 0.7 V 2 Plot Ids vs. Vds 1.5 V =4 ± Vgs = 0, 1, 2, 3, 4, 5 1 V =3 ± Use W/L = 4/2 P 0.5
gs

Ids (mA)

gs

gs

0 0 1 2

Vgs = 2 Vgs = 1

3
Vds

4

5

¨ 3.9 y 8.85 ™ 10 14 ¸ ¨ W W ! 350 © F ! Q Cox ¹© 8 L ª 100 ™ 10 ºª L
MOS devices

W ¸ ! 120 Q A / V 2 ¹ L º

CMOS VLSI Design

Slide 25

pMOS I-V
All dopings and voltages are inverted for pMOS Mobility Qp is determined by holes ± Typically 2-3x lower than that of electrons Qn ± 120 cm2/V*s in AMI 0.6 Qm process Thus pMOS must be wider to provide same current ± In this class, assume Qn / Qp = 2

MOS devices

CMOS VLSI Design

Slide 26

Capacitance
Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important ± Creates channel charge necessary for operation Source and drain have capacitance to body ± Across reverse-biased diodes ± Called diffusion capacitance because it is associated with source/drain diffusion

MOS devices

CMOS VLSI Design

Slide 27

Gate Capacitance
Approximate channel as connected to source Cgs = IoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/Qm

l silic t t i ( -t
MOS devices CMOS VLSI Design Slide 28

t

i . I)

i s l t r, I

Diffusion Capacitance
Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter ± Use small diffusion nodes ± Comparable to Cg for contacted diff ± ½ Cg for uncontacted ± Varies with process

MOS devices

CMOS VLSI Design

Slide 29

Pass Transistors
We have assumed source is grounded What if source > 0? VDD ± e.g. pass transistor passing VDD VDD

MOS devices

CMOS VLSI Design

Slide 30

Pass Transistors
We have assumed source is grounded What if source > 0? VDD ± e.g. pass transistor passing VDD VDD Vg = VDD ± If Vs > VDD-Vt, Vgs < Vt ± Hence transistor would turn itself off nMOS pass transistors pull no higher than VDD-Vtn ± Called a degraded ³1´ ± Approach degraded value slowly (low Ids) pMOS pass transistors pull no lower than Vtp
MOS devices CMOS VLSI Design Slide 31

Pass Transistor Ckts
VDD VDD VDD VDD VDD VDD

VDD VDD VSS

MOS devices

CMOS VLSI Design

Slide 32

Pass Transistor Ckts
VDD VDD Vs VDD-Vt VDD VDD VDD-Vt VDD-Vt VDD VDD VSS VDD-Vt VDD VDD

Vs

|Vt |

VDD-Vt VDD- Vt

MOS devices

CMOS VLSI Design

Slide 33

Effective Resistance
Shockley models have limited value ± Not accurate enough for modern transistors ± Too complicated for much hand analysis Simplification: treat transistor as resistor ± Replace Ids(Vds, Vgs) with effective resistance R ‡ Ids = Vds/R ± R averaged across switching of digital gate Too inaccurate to predict current at any given time ± But good enough to predict RC delay

MOS devices

CMOS VLSI Design

Slide 34

RC Delay Model
Use equivalent circuits for MOS transistors ± Ideal switch + capacitance and ON resistance ± Unit nMOS has resistance R, capacitance C ± Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width
d R/k g kC s kC kC d k s kC kC d s kC 2R/k g d k s

g

g

MOS devices

CMOS VLSI Design

Slide 35

RC Values
Capacitance ± C = Cg = Cs = Cd = 2 fF/Qm of gate width ± Values similar across many processes Resistance ± R } 6 K;*Qm in 0.6um process ± Improves with shorter channel lengths Unit transistors ± May refer to minimum contacted device (4/2 P) ± Or maybe 1 Qm wide device ± Doesn¶t matter as long as you are consistent
MOS devices CMOS VLSI Design Slide 36

Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter

A 1

Y

2 1

MOS devices

CMOS VLSI Design

Slide 37

Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C R 2C Y 1 1 C

A

2 Y

2

2C

MOS devices

CMOS VLSI Design

Slide 38

Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C R 2C 2C Y 1 1 C R C R C C 2C

A

2 Y

2

2C

C

MOS devices

CMOS VLSI Design

Slide 39

Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C R 2C 2C Y 1 1 C R C R C C 2C

A

2 Y

2

2C

C

d = 6RC
MOS devices CMOS VLSI Design Slide 40

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