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You are on page 1of 25

Introduction to Pipelined

Processors

Principle of Designing Pipeline

Processors

(Design Problems of Pipeline

Processors)

State Diagram

Shortcut Method of finding Latency

**• Forbidden Latency Set,F = {5} U {2} U {2}
**

= { 2,5}

State Diagram

• The initial collision vector (ICV) is a binary

vector formed from F such that

C = (Cn…. C2 C1)

where Ci = 1 if i F and Ci = 0 if otherwise

• Thus in our example

F = { 2,5 }

C = (1 0 0 1 0)

State Diagram

• The procedure is as follows:

1. Start with the ICV

2. For each unprocessed state,

For each bit i in the CVi which is 0, do the

following:

a. Shift CVi right by i bits

b. Drop i rightmost bits

State Diagram

c. Append zeros to left

d. Logically OR with ICV

e. If step(d) results in a new state then form a

new node for this state and join it with node

of CVi by an arc with a marking i.

• This shifting process needs to continue until

no more new states can be generated.

State Diagram

10010

State Diagram

10010 i =1

1

ICV – 10010 OR

CVi – 01001

11011 CV* 11011

State Diagram

10010 3

i =3

1

ICV – 10010 OR

11011 CVi – 00010

CV* 10010

State Diagram

10010 3

i =4

1 4

11011 10011

ICV – 10010 OR

CVi – 00001

CV* 10011

State Diagram

5

10010 3

i =5

1 4

11011 10011

ICV – 10010 OR

CVi – 00000

CV* 10010

State Diagram

5

10010 3

4

1 3

11011 10011

i =3

ICV – 10010 OR

CVi – 00010

CV* 10010

State Diagram

5

10010 3

4

1 3

4

11011 10011

i =4

ICV – 10010 OR

CVi – 00001

CV* 10011

State Diagram

5

10010 3

4

1 3

4

11011 10011

3

i =3

ICV – 10010 OR

CVi – 00011

CV* 10011

State Diagram

5+

10010 3

5+ 4

1 3

4

11011 10011

3

i =5

ICV – 10010 OR

CVi – 00000

CV* 10010

State Diagram

5+

10010 3

5+ 4 5+

1 3

4

11011 10011

3

i =5

ICV – 10010 OR

CVi – 00000

CV* 10010

State Diagram

• The state with all zeros has a self-loop which

corresponds to empty pipeline and it is possible

to wait for indefinite number of latency cycles of

the form (7),(8), (9),(10) etc.

• Simple Cycle: latency cycle in which each state is

encountered only once.

• Complex Cycle: consists of more than one

simple cycle in it.

• It is enough to look for simple cycles

State Diagram

• Greedy Cycle: A simple cycle is a greedy cycle if

each latency contained in a cycle is the minimal

latency(outgoing arc) from a state in the cycle.

• A good task initiation sequence should include

the greedy cycle.

Simple cycles & Greedy cycles

• The Simple cycles are?

• The Greedy cycles are ?

Simple cycles & Greedy cycles

• The simple cycles are (3),(5) ,(1,3,3),(4,3) and

(4)

• The Greedy cycle is (1,3,3)

State Diagram

• In the above example, the cycle that offers MAL

is (1, 3, 3) (MAL = (1+3+3)/3 =2.333)

1 2 3 4 5 6 7 8 9 10 11 12 13

Sa A1 A2 A5 A1 A2 A8 A5 A8

Sb A1 A2 A1 A2 A5 A5 A8 A8

Sc A1 A2 A1 A2 A5 A5 A8 A8

UQ: Problem

• Consider the reservation table given below

1 2 3 4 5 6 7 8 9

S1 x x

S2 x x x

S3 x

S4 x x

S5 x x

Problem

i. Find the forbidden set of latencies

ii. State the collision vector

iii. Draw the state transition diagram

iv. List simple cycles and greedy cycles

v. Calculate MAL (minimum average latency)

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