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Power Electronics

Lecture-7
Unijunction Transistor &
Programmable Unijunction Transistor

Dr. Imtiaz Hussain


Assistant Professor
email: imtiaz.hussain@faculty.muet.edu.pk
URL :http://imtiazhussainkalwar.weebly.com/

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Unijunction Transistor (UJT)
• UJT is another solid state three terminal device that can be
used in gate pulse, timing circuits and trigger generator
applications to switch and control thyristors and triacs for AC
power control applications.

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Unijunction Transistor (UJT)
• Equivalent Circuit: UJT’s have unidirectional conductivity and
negative impedance characteristics acting more like a variable
voltage divider during breakdown

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Unijunction Transistor (UJT)
• As the physical position of the p-n junction is closer to
terminal B2 than B1 the resistive value of RB2will be less than RB1.

• These two series resistances produce a


voltage divider network between the two
base terminals of the Unijunction transistor

• Since this channel stretches from B2 to B1,


when a voltage is applied across the device,
the potential at any point along the channel
will be in proportion to its position between
terminals B2 and B1.

• The level of the voltage gradient therefore


depends upon the amount of supply voltage.
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Unijunction Transistor (UJT)
• When used in a circuit, terminal B1 is connected to ground and
the Emitter serves as the input to the device.

• Suppose a voltage VBB is applied


across the UJT between B2 and B1 so
that B2 is biased positive relative
to B1.

• With zero Emitter input applied, the


voltage developed across RB1 (the
lower resistance) of the resistive
voltage divider can be calculated as:

𝑅𝐵1
𝑉𝑅𝐵1 = 𝑉
𝑅𝐵1 + 𝑅𝐵2 𝐵𝐵
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Unijunction Transistor (UJT)
• For a Unijunction transistor, the resistive ratio of RB1 to RBB is
called the intrinsic stand-off ratio (η).

𝑅𝐵1
𝜂=
𝑅𝐵1 + 𝑅𝐵2

• Typical standard values of η range


from 0.5 to 0.8 for most common
UJT’s.

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Unijunction Transistor (UJT)
• If a small positive input voltage (less than the voltage
developed across resistance RB1 is now applied to the Emitter
input terminal, the diode p-n junction is reverse biased, thus
offering a very high impedance and the device does not
conduct.

• The UJT is switched “OFF” and zero current flows.

• However, when the Emitter input voltage is increased and


becomes greater than VRB1 (or ηVBB + 0.7V, where 0.7V equals
the p-n junction diode volt drop) the p-n junction becomes
forward biased and the Unijunction transistor begins to
conduct.

• The result is that Emitter current, ηIE now flows from the
Emitter into the Base region.
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UJT Characteristics

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UJT Characteristics

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Example-1
• The intrinsic stand-off ratio for a UJT is determined to be 0.6. If
the inter-base resistance (RBB) is 10kΩ what are the values of
RB1 and RB2?

Solution

• Intrinsic stand-off ratio for a UJT is given as

𝑅𝐵1
𝜂=
𝑅𝐵1 + 𝑅𝐵2
𝑅𝐵1
0.6 =
10𝐾

𝑅𝐵1 = 6𝐾Ω
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Example-1
• Inter-base resistance (RBB) is 10kΩ
𝑅𝐵𝐵 = 𝑅𝐵1 + 𝑅𝐵2

10𝐾 = 6𝐾 + 𝑅𝐵2

𝑅𝐵2 = 4𝐾Ω

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Example-2
• A UJT has 10V between the bases. If the intrinsic stand off
ratio is 0.65, find the value of stand off voltage. What will be
the peak point voltage if the forward voltage drop in the pn
junction is .7V?
Solution
• VBB=10V, 𝜂 = 0.65, 𝑉𝐷 = 0.7𝑉
• Stand off voltage (VRB1) is given as

𝑉𝑅𝐵1 = 𝜂𝑉𝐵𝐵
𝑉𝑅𝐵1 = 0.65 × 10

𝑉𝑅𝐵1 = 6.5𝑉
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Example-2
Solution
• VBB=10V, 𝜂 = 0.65, 𝑉𝐷 = 0.7𝑉

• Peak point Voltage (VP) is given as

𝑉𝑃 = 𝜂𝑉𝐵𝐵 + 𝑉𝐷

𝑉𝑃 = 6.5 + 0.7

𝑉𝑃 = 7.2𝑉

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UJT Applications
• The most common application of a Unijunction
transistor is as a triggering device
for SCR’s and Triacs

• Other UJT applications include sawtoothed


generators, simple oscillators, phase control, and
timing circuits.

• The simplest of all UJT circuits is the Relaxation


Oscillator producing non-sinusoidal waveforms.
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UJT Relaxation Oscillator
• In a basic and typical UJT relaxation oscillator
circuit, the Emitter terminal of the Unijunction
transistor is connected to the junction of a series
connected resistor and capacitor.

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UJT Relaxation Oscillator

𝑉𝐶 = 𝑉𝐵𝐵 (1 − 𝑒 −𝑡/𝑅3𝐶 )

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UJT Relaxation Oscillator
𝑉𝐶 = 𝑉𝐵𝐵 (1 − 𝑒 −𝑡/𝑅3𝐶 )

• Discharge of the capacitor occurs when VC =Vp.

𝑉𝑃 = 𝑉𝐵𝐵 (1 − 𝑒 −𝑡/𝑅3𝐶 )

𝜂𝑉𝐵𝐵 = 𝑉𝐵𝐵 (1 − 𝑒 −𝑡/𝑅3𝐶 )

• Note: VD is ignored in above equation

1 − 𝜂 = 𝑒 −𝑡/𝑅3𝐶

𝑡
ln(1 − 𝜂) = −
𝑅3 𝐶

1
𝑅3 𝐶 ln( )=𝑡
1−𝜂 17
Example-3
• The data sheet for a 2N2646 Unijunction Transistor gives
the intrinsic stand-off ratio η as 0.65. If a 100nF capacitor
is used to generate the timing pulses, calculate the
timing resistor required to produce an oscillation
frequency of 100Hz.

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Example-3
• The timing period is given as:
1
𝑇= = 10𝑚𝑠
100

• The value of the timing resistor, R3 is


calculated as:
1
𝑅3 𝐶 ln( )=𝑡
1−𝜂

10𝑚
𝑅3 =
1
𝐶 ln( )
1−𝜂

𝑅3 = 95.23𝐾Ω

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UJT Motor Speed Control Circuit

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Example-4
• Consider the UJT relaxation oscillator
shown in figure. Assume that UJT has
following characteristics.

𝜂 = 0.63 𝑉𝑣 = 1.5 𝑉c 𝑅𝐵𝐵 = 9.2 𝐾Ω


𝑅𝐵1 = 5.8 𝐾Ω 𝑅𝐵2 = 3.4 𝐾Ω

𝐼𝑃 = 5𝜇𝐴 𝐼𝑉 = 3.5 𝑚𝐴Ω

• Find
a) VP
b) Output Frequency 𝑓
c) Prove that a 10 𝐾Ω 𝑅𝐸 is within
acceptable range
i.e 𝑅𝐸𝑚𝑖𝑛 < 𝑅𝐸 < 𝑅𝐸𝑚𝑎𝑥 21
Example-4
• Solution
a) VP

𝑉𝑝 = 𝜂𝑉𝑏𝑏 + 0.7

𝑅𝐵𝐵
𝑉𝑏𝑏 = 𝑉𝑠
𝑅1 + 𝑅1 + 𝑅𝐵𝐵

𝑉𝑏𝑏 = 22.6 𝑉

𝑉𝑝 = 0.65 × 22.6 + 0.7

𝑉𝑝 = 15.39 𝑉

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Example-4
• Solution
b) Output Frequency 𝑓
1
𝐹=
1
𝑅𝐸 𝐶𝐸 ln
1−𝜂

𝐹 = 476 𝐻𝑧

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Example-4
• Solution
c) Prove that a 10 𝐾Ω 𝑅𝐸 is within
acceptable range
i.e 𝑅𝐸𝑚𝑖𝑛 < 𝑅𝐸 < 𝑅𝐸𝑚𝑎𝑥

𝑉𝑠 − 𝑉𝑝 24 − 15.39
𝑅𝐸𝑚𝑎𝑥 = = = 1.7𝑀Ω
𝐼𝑃 5𝜇

𝑉𝑠 − 𝑉𝑉 24 − 1.5
𝑅𝐸𝑚𝑖𝑛 = = = 6.4 𝐾Ω
𝐼𝑉 3.5𝑚

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Line-Synchronized UJT Trigger Circuit for SCR

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Line-Synchronized UJT Trigger Circuit for SCR

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Programmable Unijunction Transistor (PUT)
• It is called a UJT just because its characteristics and
parameters have much similarity to that of the unijunction
transistor.
• It is called programmable because the parameters like
intrinsic standoff ratio (η), peak voltage(Vp) etc can be
programmed with the help of two external resistors.

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PUT Characteristics
• PUT characteristics is essentially a plot between the anode
voltage Va and anode current Ia of the PUT.

• Typically the anode of the PUT is


connected to a positive voltage and the
cathode is connected to the ground.

• The gate is connected to the junction of


the two external resistor R1 and R2 which
forms a voltage divider network.

• It is the value of these two resistors that


determines the intrinsic standoff ratio(η)
and peak voltage (Vp) of the PUT.
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PUT Characteristics
• When the anode to cathode voltage (Va)is increased the anode
current will also ncrease and the junction behaves like a typical P-
N junction.
• But the Va cannot be increased beyond a particular point. At this
point sufficient number of charges are injected and the junction
starts to saturate. Beyond this point the anode current (Ia)
increases and the anode voltage (Va) decreases.

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PUT Characteristics
• Beyond this point the anode current (Ia) increases and the
anode voltage (Va) decreases. This is equal to a negative
resistance scenario and this negative resistance region in the
PUT characteristic is used in relaxation oscillators. When the
anode voltage (Va) is reduced to a particular level called
“Valley Point”, the device becomes fully saturated and no
more decrease in Va is possible. There after the device
behaves like a fully saturated P-N junction.

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PUT Characteristics
• Intrinsic standoff ratio ( η) : Intrinsic standoff ratio of a PUT is
the ratio of the external resistor R1 to the sum of R1 and R2.

• It helps us to predict how much voltage will be dropped across


the gate and cathode for a given Vbb.

• The intrinsic standoff ratio can be expressed using the equation:

𝑅1
𝜂=
𝑅1 + 𝑅2

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PUT Characteristics
• Peak voltage (Vp): It is the anode to cathode voltage after which
the PUT jumps into the negative resistance region.

• The peak voltage Vp will be usually one diode drop (0.7V) plus
the gate to cathode voltage (Vg).

• Peak voltage can be expressed using the equation:

𝑉𝑝 = 𝑉𝑔 + 0.7

𝑉𝑝 = 𝑉𝑅1 + 0.7

𝑉𝑝 = 𝜂𝑉𝑏𝑏 + 0.7

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PUT Relaxation Oscillator

• Resistors R1 and R2 set the peak


voltage (Vp) and intrinsic standoff
ratio (η) of the PUT.

• Resistor Rk limits cathode current


of the PUT.

• Resistor R and capacitor C sets the


frequency of the oscillator.

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PUT Relaxation Oscillator
• When the voltage across the capacitor exceeds the peak voltage (Vp)
the PUT goes into negative resistance mode and this creates a low
resistance path from anode(A) to cathode(K).

• When the voltage across the capacitor is below valley point voltage
(Vv) the PUT reverts to its initial condition.

• The capacitor starts to charge again and the cycle is repeated. This
series of charging and discharging results in a sawtooth waveform
across the capacitor as shown in the figure below.

1
𝐹=
1
𝑅𝐶 ln
1−𝜂

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END OF LECTURE-7

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