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8086 Microprocessor Architecture -

Programmable view
Lecture No.2
Mohammed D. Ali
3rd stage
2018-2019
Features of 8086 MP
• It is a 16-bit μp.
• 8086 has a 20 bit address bus can access up to 220
memory locations (1048576 ≈ 1 MB).
• It can support up to (65536 ≈ 64K) I/O ports.
• It provides 14, 16 -bit registers.
• Word size is 16 bits and double word size is 4
bytes (32 bits).
• It has multiplexed address and data bus AD0-
AD15 and A16 – A19.
Features of 8086 MP
• 8086 is designed to operate in two modes,
Minimum and Maximum.
• It can prefetches up to 6 instruction bytes from
memory and queues them in order to speed up
instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package.
• Address ranges from 00000H to FFFFFH.
Internal architecture of 8086
• 8086 has two blocks Bus Interface Unit BIU, and
Execution Unit EU.
• The BIU handles with many functions such as:
o Instruction fetching.
o Reading/Writing data for memory.
o Input/ output data for I/O ports.
o Instruction queuing.
o Address generation.
• EU executes instructions from the instruction
system byte queue.
Intel 8086 Internal Architecture
Intel 8086 Internal Architecture
• BIU contains many components to implement the
above functions such as:
o Segment registers
o Instruction pointer
o The address generation adder
o Bus control logic
o Instruction queue
• EU contains the following parts:
o General registers
o Operand register
o Arithmetic Logic Unit ALU
o Flags/ Status register.
EXECUTION UNIT
• Decodes instructions fetched by the BIU
• Generate control signals,
• Executes instructions.
The main parts are:
• Control Circuitry
• Instruction decoder
• ALU
• General purpose register
EXECUTION UNIT – General Purpose Registers
16 bits

8 bits 8 bits

AH AL
AX Accumulator

BH BL
BX Base
CH CL
CX Count
DH DL
DX Data
SP
Stack Pointer
Pointer BP
Base Pointer
SI
Source Index
Index
DI
Destination Index
EXECUTION UNIT – General Purpose Registers
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic

AH Byte multiply, byte divide

BX Store address information

CX String operation, loops

CL Variable shift and rotate

DX Word multiply, word divide, indirect I/O


(Used to hold I/O address during I/O instructions. If the result is more than
16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored in DX register)
Pointer And Index Registers
• used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a
physical address is the Stack Segment (SS-will be discussed
under the BIU)
• The index registers (SI & DI) and the BX generally default to
the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
Pointer And Index Registers
• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI register
points to memory locations in the data segment which
is addressed by the DS register. Thus, SI is associated
with the DS in string operations.
• DI: Destination Index register
– is also required for some string operations.
– When string operations are performed, the DI register
points to memory locations in the data segment which
is addressed by the ES register. Thus, DI is associated
with the ES in string operations.
• The SI and the DI registers may also be used to access
data stored in arrays
EXECUTION UNIT – Flag Register
• A flag is a flip flop which indicates some
conditions produced by the execution of an
instruction or controls certain operations of the
EU .
• In 8086 The EU contains
o a 16 bit flag register
o 9 of the 16 are active flags and remaining 7 are
undefined.
o 6 flags indicates some conditions- status flags
o 3 flags –control Flags
U U U U OF DF IF TF SF ZF U AF U PF U CF

Sign Auxiliary Carry


Interrupt Trap Zero Parity
Over flow Direction
U - Unused
EXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.

Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is not zero
Sign (SF) Holds the sign of the result after an arithmetic/logic instruction
execution. S=1; negative, S=0 positive.
EXECUTION UNIT – Flag Register
Flag Purpose
A control flag.
Trap (TF) Enables the trapping through an on-chip debugging
feature. TF =1 interrupts after each step, TF =0 no
interrupts after each step.
A control flag.
Interrupt (IF) Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
A control flag.
Direction (DF) It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions. DF=1
decrement, DF=0 increament.
Overflow occurs when signed numbers are added or
Overflow (OF) subtracted. An overflow indicates the result has exceeded
the capacity of the Machine. OF =1 the result has more bits
Execution unit – Flag Register
• Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
BUS INTERFACE UNIT (BIU)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)
THE QUEUE (Q)
• The BIU uses a mechanism known as an
instruction stream queue to implement a
pipeline architecture.
• This queue permits pre-fetch of up to 6 bytes of
instruction code. Whenever the queue of the BIU
is not full, it has room for at least two more bytes
and at the same time the EU is not requesting it
to read or write operands from memory, the BIU
is free to look ahead in the program by pre-
fetching the next sequential instruction.
Segmented Memory
00000
The memory in an 8086/88 based
system is organized as segmented
memory.
Code segment (64KB)

The CPU 8086 is able to address


Data segment (64KB)

1 MB
1Mbyte of memory.
Extra segment (64KB)
The Complete physically available
memory may be divided into a Stack segment (64KB)
number of logical segments.
The size of each segment is 64 KB
A segment may be located any FFFFF
where in the memory 18
Segmented Memory
• The 4 segments are Code, Data, Extra and Stack
segments.
• Each of these segments can be used for a specific
function.
– Code segment is used for storing the instructions.
– The stack segment is used as a stack and it is used to store
the return addresses.
– The data and extra segments are used for storing data byte.
• The 16 bit contents of the segment registers in the
BIU actually point to the starting location of a
particular segment.
• Segments may be overlapped or non-overlapped
Segment registers
• In 8086/88 the processors have 4 segments
registers
• Code Segment register (CS), Data Segment
register (DS), Extra Segment register (ES) and
Stack Segment (SS) register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16
bit address of the starting address of the
corresponding segments.
Physical Memory Address Generation

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)


Physical Memory Address Generation
• The following examples shows the CS:IP scheme
of address formation:
CS 34BA IP 8AB4 Code segment
34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D654

34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F
Segment and Address register combination

• CS:IP

• SS:SP SS:BP

• DS:BX DS:SI

• DS:DI (for other than string operations)

• ES:DI (for string operations)


8086 Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data


already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
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Microprocessor
Functional blocks
Various conditions of the
Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus


internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for


internal and external Decodes instructions; sends
operations of the information to the timing and
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microprocessor control unit
8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Dedicated Adder to generate
20 bit address

Four 16-bit segment


registers

Code Segment (CS)


Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

27 Segment Registers >>


8086 Microprocessor
Execution Unit (EU)
Architecture Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
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8086 Microprocessor Common signals

Pins and Signals


AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are


multiplexed with data.

When AD lines are used to transmit


memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines


the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are


multiplexed with status signals

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8086 Microprocessor
Common signals
Pins and Signals
BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most


significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the


processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.


It is an output signal.
It is active when low.
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8086 Microprocessor
Common signals

Pins and Signals TEST

𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’


instruction.

8086 will enter a wait state after


execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.

This is used to synchronize an external


activity to the processor internal
operation.

READY

This is the acknowledgement from the


slow device or memory that they have
completed the data transfer.

The signal made available by the devices


is synchronized by the 8284A clock
generator to provide ready input to the
8086.
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The signal is active high.
8086 Microprocessor
Common signals

Pins and Signals RESET (Input)

Causes the processor to immediately


terminate its present activity.

The signal must be active HIGH for at


least four clock cycles.

CLK

The clock input provides the basic timing


for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled


during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally


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synchronized.
8086 Microprocessor
Min/ Max Pins
Pins and Signals
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the


microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work


in multi-processor or co-processor
configuration.

Minimum or maximum mode operations


are decided by the pin MN/ MX(Active
low).

When this pin is high 8086 operates in


minimum mode otherwise it operates in
Maximum mode.

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8086 Microprocessor

Pins and Signals Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied


to VCC (logic high)

8086 itself generates all the bus control signals

Minimum mode signals

(Data Transmit/ Receive) Output signal from the


processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor


used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the


address and data lines using external latches

Used to differentiate memory access and I/O


access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever


processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt


request is accepted by the processor, the output is
34 low on this line.
8086 Microprocessor
Minimum mode signals
Pins and Signals
Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied


to VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters


as a request to grant the control of the bus.

Usually used by the DMA controller to get the


control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the


processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the


processor accepts HOLD.

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8086 Microprocessor
Maximum mode signals
Pins and Signals During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)

Pins 24 -31 are reassigned

Status signals; used by the 8086 bus controller to


generate bus timing and control signals. These are
decoded as shown.

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8086 Microprocessor
Maximum mode signals
Pins and Signals
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)

Pins 24 -31 are reassigned

(Queue Status) The processor provides the status


of queue in these lines.

The queue status can be used by external device to


track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as


shown in the table.

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8086 Microprocessor
Maximum mode signals
Pins and Signals
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)

Pins 24 -31 are reassigned

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