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Presented by : Subin Mathew RASET Cochin

Programmable Read Only Memory (PROM) fuse programming n- address i/p can implement n i/p logic fun. Problem: Area efficiency. Programmable Logic Array (PLA) Programmable AND plane followed by programmable or wired OR plane. Sum of product form Problem : Two level programming adds delay

NEXT Programmable Array Logic (PAL) Programmable AND plane and fixed OR plane. Flexible comparably. All these PLA and PAL are Simple Programmable Logic Devices (SPLD). Problem: Logic plane structure grows rapidly with number of inputs

Problem : Extending to higher density difficult Less flexibility .NEXT To mitigate the problem Complex Programmable Logic Devices (CPLD) programmably interconnect multiple SPLDs.


Topics covered:‡ FPGA Overview ‡ Logic Block ‡ FPGA Routing Techniques ‡ Programming Methodology ‡ FPGA Design Flow .FPGA A Field Programmable Gate Array (FPGA) is a Programmable Logic Device(PLD) with higher densities and capable of implementing different functions in a short period of time.

Compact design User can configure Intersections between the logic blocks y The function of each block y .FPGA OVERVIEW 2-D array of logic blocks and flip-flops with programmable interconnections.

Why do we need FPGAs? WORLD OF INTEGRATED CIRCUITS Full-Custom ASICs Semi-Custom ASICs User Programmable PLD FPGA .

WHICH WAY TO GO? ASICs High performance Low power Low cost in high volumes FPGAs Low development cost Short time to market Reprogrammable .

OTHER FPGA ADVANTAGES Manufacturing cycle for ASIC is very costly. lengthy and engages lots of manpower Mistakes not detected at design time have large impact on development time and cost FPGAs are perfect for rapid prototyping of digital circuits Easy upgrades like in case of software Unique applications .

two types of Blocks : Fine Grain Logic Blocks Coarse Grain Logic Blocks . According to granularity. Granularity: is the hardware abstraction level.LOGIC BLOCKS Purpose: to implement combinational and sequential logic functions. Logic blocks can be implemented by:‡ Transistor pairs ‡ Multiplexers ‡ Look up tables( LUT) ‡ Wide fan-in AND-OR structure.

FINE GRAIN 1. . The Cross Point FPGA Transistors are interconnected. Logic block is implemented using transistor pair tiles.

Plessey FPGA ::- ‡ 2-input NAND gate forms basic building block ‡ Static RAM programming technology .2.

FINE GRAIN Advantage: Blocks are fully utilized. . Disadvantage: Disadvantage: Require large numbers of wire segments and programmable switches. Need more area.

COARSE GRAIN LOGIC BLOCKS Many types exists according to implementations Multiplexer Based and Look-up-Table Based are most common 1. The Xilinx Logic Block: y y y y y A SRAM function as a LUT. Address line of SRAM as input Output of SRAM gives the logic output k-input logic function =2^k size SRAM K-i/p LUT gives 2^2^k logic functions .

Advantage: High functionality y k inputs logic block can be implemented in no. of ways y Disadvantage: y Large no of memory cells required if i/p is large .

Altera logic block:Wide fan-in y Up to 100 i/p AND gate fed into OR gate with 3-8 i/ps y Advantage:Few logic block can implement the entire functionality y Less area required y Disadvantage:If i/ps are less. usage density of block will be low y Pull up devices consume static power y .2.

So look the example .EFFECTS OF GRANULARITY ON FPGA DENSITY AND PERFORMANCE Tradeoff Granularity increase -> Blocks less More Functional Blocks-> more area Area is normally measured by total number of bits needed to implement the design.


logic blocks etc. Routing decides logic block density and area consumed Different routing techniques are:y Xilinx Routing architecture y Actel routing methodology y Altera routing methodology .FPGA ROUTING TECHNIQUES Comprises of programmable switches and wires Provides connection between I/O blocks.

Xilinx Routing architecture connections are made through a connection block. SRAM is used to implement LUT. So connection sites are large Pass transistors for connecting output pins multiplexers for input pins. wire segments used are:y general purpose segments y Direct interconnect y long line y clock lines .

Routing is flexible. .Actel routing methodology more wire segments in horizontal direction. i/p & o/p vertical tracks can make connection with every horizontal track. Drawback:more switches are required => more capacitive load.

Altera routing methodology It has two level hierarchy. first level => 16 or 32 of the logic blocks are grouped into a Logic Array Block(LAB) connections are formed using EPROM Second level=> LABs are interconnected using Programmable Interconnect Array(PIA) .

Various programming techniques are:y SRAM programming technology y Floating Gate Programming y Antifuse programming methodology . size etc. parasitic capacitance.PROGRAMMING METHODOLOGY Electrically programmable switches are used to program FPGA Properties of programmable switch determine onresistance. volatility. reprogrammability.

SRAM programming technology Use Static RAM cells to control pass gates or multiplexers. 1= closed switch connection 0= open For mux. is used Disadvantage ‡ ‡ SRAM volatile Requires large area . Advantage ‡ ‡ Fast re-programmability Standard IC fabrication Tech. SRAM determines the mux input selection process.

The charge is removed by UV light Advantage:Advantage:-No external permanent memory is needed to program it at power-up Disadvantage:Disadvantage:y Extra processing steps y Static power loss due to pull up resistor and high on resistance .Floating gate programming Tech used in EPROM and EEPROM devices is used Switch is disable by applying high voltage to gate-2 between gate-1 and drain.

Antifuse programming methodology 2 terminal device with an un programmed state present very high resistance. Advantage: Small size Low series resistance and low parasitic capacitance . By applying high voltage create a low resistance link.


Logic is implemented using multiple levels of lower fan-in gates.WHY BETTER ? FPGA programmed using electrically programmable switches Routing architectures are complex. and draw more power. . Shorter time to market Ability to re-program in the field to fix bugs FPGA DISADVANTAGE FPGAs are generally slower than their applicationspecific integrated circuit (ASIC) Can't handle as complex a design.

The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput. Applications of FPGAs include DSP. .APPLICATION Reconfigurable computing. software-defined radio.

. and other verification methodologies. Once the design and validation process is complete. the binary file generated used to configure the FPGA. using an electronic design automation tool. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route.FPGA DESIGN AND PROGRAMMING To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design. place and route results via timing analysis. The user will validate the map. simulation. Then. a technology-mapped net list is generated.