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Antenna effect

Antenna effect
Modern wafer processing uses ‘Plasma etch’ (or ‘dry etch’). Plasma is
an ionized/reactive gas used to etch.
It allows super control of pattern (shaper edges / less undercut) and
also allows several chemical reactions that are not possible in
traditional (wet) etch. Apart from this, several unwanted things happen
just because of several plasma processing steps. One of them is the
charging damage.
Plasma charging damage refers to the unintended high-field stressing
of the gate-oxide in MOSFET during plasma processing.
Antenna effect in cmos layout

A side effect of the manufacturing process that leads to damaged parts is

known as the antenna effect. Under certain conditions, plasma etchers or
ion implanters induce charge onto various structures that connect to a gate
of a transistor. The induced charge threatens to overstress and irreparably
damage the thin gate oxides of the transistor, causing unreliable operation.
Charge is readily induced during the manufacturing process if a structure
is built in such a way that it acts like an antenna.
As the gate size gets smaller and more metals are added to a chip, and
as process engineers reduce the thickness of the oxides, the antenna effect
can have a greater impact on the yield of a wafer
How to eliminate the antenna effect

1. Change the order of the routing layers. If the gate(s) immediately connects to the highest
metal layer, no antenna violation will normally occur. This solution is shown in Figure
2. Add vias near the gate(s), to connect the gate to the highest layer used. This adds more
vias, but involves fewer changes to the rest of the net. This is shown in Figure (b).
3. Add diode(s) to the net, as shown in Figure (c). A diode can be formed away from a
MOSFET source/drain, for example, with an n+ implant in a p-substrate or with a p+
implant in an n-well. If the diode is connected to metal near the gate(s), it can protect the
gate oxide. This can be done only on nets with violations, or on every gate (in general by
putting such diodes in every library cell). The "every cell" solution can fix almost all
antenna problems with no need for action by any other tools. However, the extra
capacitance of the diode makes the circuit slower and more power hungry.
How to eliminate the antenna effect
Design Solution to reduce Antenna Effects

1. Router options Break signal wires and route to upper metal layers by jumper
insertion All metal being etched is not connected to a gate until the last metal
layer is etched.
2. Dummy transistors Addition of extra gates will reduce the capacitance ratio.
PFETs more susceptible than NFETs Problem of reverse Antenna Effects.
3. Embedded Protection Diode Connect reverse biased diodes to the gate of
transistor (during normal circuit operation, the diode does not affect functionality)
4. Diode insertion after placement and route Connect diodes only to those layers
with antenna violations. One diode can be used to protect all input ports that are
connected to the same output ports.
Design Solution to reduce Antenna Effects
Jumper Insertion Breaks Up a LongWire

jumper insertion is performed automatically during

the routing. After detailed routing, you can fix
antenna violations manually by inserting jumpers by
using commands corresponding to the tool you are
using. When you execute those commands, tool
detects and fixes antenna violations using jumpers
and a tailored ripup and reroute strategy
Diode insertion
There are two points in the design flow where you can insert
diodes to fix antenna violations. Inserting Diodes Before
Detailed Placement Normally, the diode is added only to the
pins that need it. The antenna checker is called for each pin in
question to decide first, if the pin has antenna violations and
second, if a jumper has failed in the area of the pin because the
area is blocked and a large enough hole does not exist.
Inserting Diodes After Detailed Placement After detailed
routing, the antenna violations can still exist for various
reasons. For example, there can be too much congestion to
insert a jumper or the diffusion strengths of the output pins are
too weak. In these cases, diode insertion is a viable choice. The
semiconductor manufacturer generally provides the gate area
or size, and the antenna checker calculates the appropriate
wire area using the wire (charge) accumulation method
specified by the manufacturer
Diode insertion
Diode Inserted Near a Logic Gate Input Pin As shown in Figure,
diode insertion near a logic gate input pin on a net provides a discharge path to the
substrate so that built-up charges cannot damage the transistor gate.
Unfortunately, diode insertion increases cell area and slows timing due to the
increase of logic gate input load. Moreover, diode insertion is not feasible in regions
with very high placement utilization.
In most of the tools, diode insertion is performed automatically when you use the
routing command.
You can manually insert diodes using the corresponding tool’s commands.