Data Converters Sample-and-Hold Professor Y.

Chiu
EECT 7327 Fall 2014

Sample-and-Hold (S/H) Basics

–1–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

ZOH vs. Track-and-Hold (T/H)

V(t)
• Zero acquisition time
• Infinite bandwidth
• Not realistic
0 T 2T t
T

V(t)
• T/2 acquisition time
• Finite bandwidth
H T H T H T H T H T
• Practical
0 T 2T t
T/2

–2–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

A Simple T/H (Top-Plate Sampling)

Ф
RS Ron
Vo PMOS
NMOS
Vi CS VTp VTn

CMOS
W
1
Ron  μCox VDD  Vth  Vi  0 Vi VDD
L

• MOS technology is naturally suitable for implementing T/H

• The lowpass SC network determines the tracking bandwidth
• Non-idealities: signal-dependent Ron, charge injection, aperture, etc.

–3–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Tracking Bandwidth (TBW)

RS Ron Ron

Vi CS Vo

TBW  1 RS  Ron CS 0 Vi VDD

• Tracking bandwidth determines how promptly Vo can follow Vi

• Typically TBW is many times greater than the max signal bandwidth
• What’s wrong with the concept of “linear filtering” if Ron is constant?

–4–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Dispersion
|H(jω)|
1 • Magnitude response
• Non-uniform phase delay
• Non-uniform group delay
0 ω0 ω

Phase delay :
H(jω)
ω0 ω H jω 
0 t p ω   
ω
-45° Group delay :

-90° t g ω   
d
H jω
dω

–5–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Dispersion
RS Ron

Vi CS Vo

t t

• Waveform is not very sensitive to the lowpass magnitude response as long

as the signal bandwidth is on the order of TBW
• Waveform distortion is mainly due to non-uniform phase and group delays

–6–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Signal-Dependent Ron
Ф
RS Ron
Vo PMOS
NMOS
Vi CS VTp VTn

CMOS
W
1
Ron  μCox VDD  Vth  Vi  0 Vi VDD
L

• Signal-dependent Ron → signal-dependent TBW → extra waveform

distortion
• Neither signal-dependent Ron nor dispersion is of concern if TBW is
sufficiently large (>> fin, depending on the target accuracy)

–7–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Ideal T/H

V(t)

Hold Track Hold t

• Sufficient tracking bandwidth → negligible tracking error

• Well-defined sampling instant (asserted by clock rising/falling edge)
• Zero track-mode and hold-mode offset errors

–8–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

T/H Errors (Track Mode)

V(t)

δ2
δ1
Droop

Δt
Hold Track Hold t

• Finite tracking bandwidth → tracking error, T/H memory

• Track-mode offset, gain error, and nonlinearity

–9–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Acquisition Time (tacq)

RS Ron
Accuracy tacq

Vi CS Vo 1% (7b) ≥ 5t

0.1% (10b) ≥ 7t

1
τ  RS  Ron CS 0.01% (13b) ≥ 9t
TBW

1 L2 L2
Ron   
μCox
W
VDD  Vth  Vi  μC ox WL VDD  Vth  Vi  μQch
L

Short L, thin tox, large W, large Vov, and small Vi help reduce Ron

– 10 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

T/H Errors (T-to-H Transition)

V(t)

δ2
δ1
Droop

Δt
Hold Track Hold t

• Pedestal error (often signal-dependent) resulted from switch turn-off

nonidealities (clock feedthrough and charge injection)
• Aperture delay – the delay Δt b/t hold command and hold action
• Aperture jitter – the random variation in Δt (i.e., sampling clock jitter)
– 11 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Switch Non-Idealities
Ф

VDD Vin+Vth
Zi Cgs Cgd
Vout Ф
0
Vin Qch CS
Switch on Switch off

Clock feedthrough (CF) Charge injection (CI)

Cgs Cox WL VDD  Vth  Vin 

ΔV   ΔV  
2Cgs  CS 
Fast turn-off VDD
Cgs  CS
Cgs
Slow turn-off ΔV   Vin  Vth  ΔV  0
Cgs  CS

– 12 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Pedestal Error of Top-Plate T/H

Slow turn-off:
Vo  1 ε   Vi  Vos

 Cgs  Cgs
Vo   1 V 
 C  C  i C  C th
V
 gs S  gs S

Fast turn-off:
Vo  1 ε   Vi  Vos

 1 Cox WL   Cgs 1 Cox WL 

 2 C  C  i  C  C DD 2 C  C  DD
Vo   1 V  V  V  Vth  
 gs S   gs S gs S 

Watch out for nonlinear errors!

– 13 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Speed-Accuracy Tradeoff of T/H

1 Q ch
Pedestal error: ΔV 
2 CS

1 μQ
TBW: TBW   2 ch
RonCS L CS

ΔV 1 Qch L2CS L2
Therefore:   
TBW 2 CS μQch 2μ

Technology scaling improves T/H performance!

– 14 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Aperture Delay (Δt)

CH 1
Φ1
Vin Φ1

Φ2
CH 2

Φ2

• Fixed aperture delay is usually not of problem in a single-path T/H

• Non-uniform aperture delays among time-interleaved T/H paths cause
significant errors (Δt1, Δt2… are also called sampling clock skew)

– 15 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Aperture Jitter

V(t)
dV
dt
δV

δt
Track Hold t

Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter analysis of high-speed

sampling systems,” IEEE Journal of Solid-State Circuits, vol. 25, issue 1, pp. 220-
224, 1990.

– 16 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Aperture Jitter
Vi  t   Asin ω  t  δt  
 Asin  ωt   cos  ωδt   Acos  ωt   sin  ωδt 
  ωδt    ωδt   ωδt 
 Asin  ωt   1 sin2    Acos  ωt   2sin   cos  
  2   2   2 
 Asin  ωt   ωδt  Acos  ωt  for small δt

εt   Vi t   Asinωt  ωδt  Acosωt  " Cyclostati onary"

T 2
A 2ω 2 A 2ω 2σ t
ε t   δt   Aω  cosωt dt 
1
 δt 
2 2 2 2

T0 2 2

A2  A 2ω2σ t 2  1
 SNR 
2


 2
 2 2
 ωσ
 t

– 17 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Aperture Jitter
140
 = 0.1ps
t
120  = 1ps
t
 = 10ps
t
 = 100ps
100 t
SNR [dB]

80

60

40

20
SNR  20  LOG10 ωσt 
0 6 7 8 9
10 10 10 10
Input Freq [Hz]

– 18 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

T/H Errors (Hold Mode)

V(t)

δ2
δ1
Droop

Δt
Hold Track Hold t

• Hold-mode droop caused by off-switch/diode/gate leakage

• Hold-mode input feedthrough (i.e., due to capacitive coupling)

– 19 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Evaluating T/H Performance

2
 1 kT
VN   4kTR  df 
2
kT/C noise: 0 1 j2π  f  RC S CS
T = 300K

CS √kT/C
100pF 6.4μV
2
Vi
SNDR  1pF 64μV
SNDR: A 2ω 2 2
VN  δt  Vε
2 2

2 10fF 640μV

Noise Distortion
Jitter

– 20 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

MOS S/H Techniques

– 21 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Simple Top-Plate Sampling

Ф
RS
Vo
Vi CS

Pros
• Simple, minimum number of devices
• Potentially wideband, zero track-mode offset
Cons
• Signal-dependent tracking bandwidth
• Signal-dependent charge injection and clock feedthrough
• Signal-dependent aperture delay (sampling point)

– 22 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Signal-Dependent Aperture Delay

VDD
Vi+Vth(Vi)
Vi  t   Asin  ωt 
Ф   V  t  
Vth(Vi) Vo  t   Asin ω  t  i  
0   SR  
Switch on Switch off

• Non-uniform sampling due to signal-dependent aperture delay causes

distortion in top-plate S/H
• Sharp clock edge and small Vin mitigate the delay variation

– 23 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Signal Distortion
  V 
Vo  t   Asin ω  t  i  
  SR  
 V   V 
 Asin  ωt   cos  ω i   Acos  ωt   sin  ω i 
 SR   SR 
V V
 Asin  ωt   ω i  Acos  ωt  for small i
SR SR
V
ε t   Vi t   Vo t   ω i  Acosωt 
SR
Asinωt  ω 1 2
ε t   ω  Acosωt    A sin2  ωt  ← 2nd-order
SR SR 2
2
 A 2ω 
 
 SDR 
A2  2  SR   4  SR
2

2 2 A 2ω 2

– 24 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

CMOS Switch

Ron
Ф PMOS
NMOS
Vi Vo VTp VTn

CS
Ф CMOS

0 Vi VDD

• Ron still depends on Vin and is sensitive to N/P mismatch

• Large parasitic cap due to PMOS switch for symmetric Ron
• Clock rising/falling edge alignment

– 25 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Clock Bootstrapping

Ron
Φ Φ

VDD
In Out
M1

0 Vi VDD

• Constant gate overdrive voltage VGS = VDD for the switch

• Ron is not dependent on Vin to the first order (body effect?)
• NMOS device only with less parasitic capacitance

– 26 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Clock Bootstrapping
VDD
Φ
M5 M6 M2

M4 M3
C1 C2 C Φ
Φ
Φ Φ
Out
M1
Φ
Φ In
VSS

Ref: A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC,”
IEEE Journal of Solid-State Circuits, vol. 34, issue 5, pp. 599-606, 1999.

– 27 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Clock Bootstrapping (Φ=0)

VDD

Φ
Φ M2

M3
Φ
C Φ
Φ Φ
Out
M1
Φ
Φ In
VSS

– 28 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Clock Bootstrapping (Φ=1)

VDD

Φ
Φ M2

M3
Φ
C Φ
Φ Φ
Out
M1
Φ
Φ In
VSS

– 29 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Dummy Switch

Ф Ф

Vi Vo
W W
L CS 2L

• Initial size of dummy chosen with the assumption of a 50/50 split of

Qch; usually (W/L)dummy < ½(W/L)switch in practice
• The nonlinear dependence of CI on Zi, CS, and clock rise/fall time
makes it difficult to achieve a precise cancellation
• Ф_ rising edge must trail Ф falling edge

– 30 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Balanced Switch + Dummy

Ф Ф
• TBW
Vi Vo
W W • Parasitics
CS L CS 2L

Ref: L. A. Bienstman and H. J. De Man, “An eight-channel 8 bit microprocessor

compatible NMOS D/A converter with programmable scaling,” IEEE Journal of Solid-
State Circuits, vol. 15, issue 6, pp. 1051-1059, 1980.

– 31 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Fully-Differential T/H
Ф E.g.

Vi+ Vo+ fin 0.5GHz

M1 CS+ VDD 1.8V
tf 0.1ns
Vi- Vo- A (Vin) 0.5V
M2 CS- SDR (SE) 20-30 dB
SDR (DF) 40-50 dB

• All even-order distortions cancelled, including the signal-dependent

aperture delay-induced distortion
• Actual cancellation limited by P/N mismatch (1-10% typically)

– 32 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Bottom-Plate Sampling
Ф
CS X
Vi
Фe Ф
Фe
Ф

• AC-ground switch opens slightly earlier than input switches

• Signal-independent CF and CI of switch Φe to the first order!
• Input switch can be further bootstrapped
• Typical for applications of more than 8-bit resolution

• Less tracking bandwidth due to more switches in series

• Signal swing at node X is not entirely zero!

– 33 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Sample-and-Hold Amplifier
(SHA)

– 34 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Inverting SHA
CH+

Ф1 Ф1 Ф1 Ф1e
CS+ Ф2
Vi+ Vo+
Ф2 Ф1e
Ф2
Vi- Vo-
CS- Ф2
Ф1 Ф1
T H

CH-

• Inverting, closed-loop gain determined by the ratio CS/CH

• CMOS or bootstrapped switches are required when passing signals
with large swing (where?)

– 35 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Inverting SHA (Track-Mode)

CH+

Ф1 Ф1
CS+
W
Vi+ L/2
W
Ф1e Ф1e Ф1e
L W
Vi- L/2
CS-
Ф1 Ф1

CH-

• CF and CI are independent of Vin and cancelled differentially

• Φ1e switch is equivalent to two switches of half channel length →
faster, less CF and CI

– 36 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Inverting SHA (Hold-Mode)

CH+

C S+ Ф2
Vo+
• CM?
Ф2
Vo- • DM?
C S- Ф2

CH-

• For 1X gain (CS = CH), the feedback factor is about 1/2

• Floating switch Φ2 in hold-mode → flexible input common mode
• Useful for single-ended to differential conversion

– 37 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Differential Mode
CH+
DM half circuit
Ф2
CS + Ф2 CH
Vo+
Ф2
Vo-
 CS

Vo+
Ф2
C S- Ф2 Vi,dm Adm

CH-

• DM charge transfer is complete

– 38 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Common Mode
CH+
CM half circuit

Ф2
CS + Ф2
CH
+
Vo
Ф2
Vo-
 CS

-
Vo+
CS Ф2 Vi,cm Acm

CH-

• CM charge is not transferred!

– 39 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014

Flip-Around SHA

Ф1 Ф1 Ф1e
CS+ Ф1e Ф2
Vi+ Vo+
Ф2
Vi- Vo-
CS- Ф1e Ф2
Ф1 T H

• Non-inverting, 1X closed-loop gain

• Close-to-unity feedback factor in hold mode
• CF/CI independent of Vin and cancelled differentially

– 40 –