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DFT ( Design For Test ) For Advance Users

 Why to Test

 Introduction to DFT

 Why DFT

 Scan
 What is scan
 Scan Architecture
 Scan Design Rules (General Consideration)
 Fault Modeling
 Types of Fault Model

 ATPG (Automatic Test Pattern Generation)

 BIST (Built-In Self Test )

 JTAG Boundary Scan

Why to Test ?

 The process of determining whether a device or circuit

 Is functioning correctly, or
 Is defective
 Device can be defective because it does not function

 As designed, or
 As specified
 Guarantee IC quality

 Not only working devices also reliable devices

 Enhance Profit

 Reduce test cost

Why to Test ? (Cont’d..)
 Verify Manufacturing of Circuit
 Improve System Reliability
 Diminish System Cost
 Cost of repair
 Goes up by an order of magnitude each step away from the manufacturing efforts


IC Test Board System Warranty

Test Test Repair
Faults, Errors and Failures

 Fault
 A physical defect within a circuit or a system
 May or may not cause a system failure
 Error
 Manifestation of a fault that results in incorrect circuit (system)
outputs or states
 Caused by faults
 Failure
 Deviation of a circuit or system from its specified behavior
 Caused by an error

 Fault ---> Error ---> Failure

Source of problems
 Design problems
 Logic Design Incorrect
 Physical Design Incorrect
 Manufacturing problems
 Processing Faults
 missing contact windows
 parasitic transistors
 Material Defects
 bulk defects (cracks, crystal imperfections)
 surface impurities
 Electrical Defects
 Shorts (Bridging Faults)
 Opens
 Transistor Stuck-On/Open
DFT Concerns….
 Logical Defects
 Logical Stuck-at 0/1
 Slower Transition (Delay Faults)
Coverage Calculations

Test Coverage : Test coverage is a measure of test quality, which consists of the
percentage of all testable faults that the test pattern set tests.

Test coverage = detected faults / testable faults

 Fault Coverage : The fault coverage is the percentage of faults detected among
the total faults tested. The higher the fault coverage,the better the test pattern
separates a faulty circuit from a fault-free circuit.

Fault coverage = detected faults/(testable + untestable )

Testing and Quality

 Yield is the fraction of good chips produced during manufacturing

 Quality of shipped part is a function of yield Y and the test (fault) coverage
Defect Level

 Defect Level
 is the fraction of bad parts among the parts that pass all tests
and are shipped

Y = Yield
T = Fault coverage
Design Levels from Testability Perspective
Why Testing Is Difficult ?

 Test application time can be exploded for exhaustive testing of VLSI

 For a combinational circuit with 50 inputs, we need 250= 1.126 x 1015 test
 Assume one test per 10-7sec, it takes 1.125x108sec = 3.57 yrs. to test such a
 Test generation for sequential circuits are even more difficult due to the lack
of controllability and observability at flip-flops
 Functional testing may NOT be able to detect the physical faults
Introduction to DFT (Design For Testability)
What is DFT ?

An action of placing features in a chip design during the design process

 To enhance the ability to test the design

 Generate vectors
 Achieve a measured quality level
 Reduce the cost-of-test
 Provide controllability
 Provide Observability
 Controllability : Ability to place nets, nodes, gates, or sequential elements to a
known logic state

 Observability : Ability to observe nets, nodes, gates, or sequential elements

after they have been driven to a known logic state
Why DFT ?

 Structural testing of 4 bit full adder circuit would take less than 16 patterns to
test using ATPG
 Functional testing would require 24 =16 patterns to test circuits
 Gives an additional design check
 Quantifiable test metrics
 Faster generation of working test patterns (automated)
 Faster ramp-to-volume production
What is Scan ?

 Scan is a method to make circuit easily testable and accessible

 Scan allows to have controllability and observability for FFs
 It tests combinational circuits using sequential logic
 With Scan, All FFs will form a chain like a shift register
 With Scan, a synchronous sequential circuit works in two modes
Normal mode and Test mode:
Different Scan Architectures

 Three main scan design architectures

 Multiplexed flip-flop Scan

 Clocked scan
 Level-sensitive scan design (LSSD)
Why Fault Model ?
 Mathematical model of faulty behavior
 Can be used to assess the compliance of a circuit to various criteria.
For example,
 Structural compliance can be verified by using a stuck-at fault model
 Timing compliance can be verified by using a delay fault model
 Current leakage compliance can be verified by using a bridging fault model

 Identifies target faults

 Models faults which are most likely to occur
 Limits the scope of test generation
 Makes effectiveness measurable by experiments
 Fault coverage can be computed for specific test patterns to reflect its
 Makes analysis possible
Fault modeling

 Electrical defects
 Shorts (Bridging Faults)
 Opens
 Transistor Stuck-On/Open
 Resistive Shorts/Opens
 Change in Threshold Voltages
 Logical defects
 Logical Stuck-at 0/1
 Slower Transition (Delay Faults)
 AND-bridging, OR-bridging
Fault Model Types Commonly Used To Guide Test Generation

 Stuck-at Fault model

 Current Based Fault Model (IDDQ Measurement)
 Delay Fault Model (Transition and path delay )
 Bridging Fault Model
Single Stuck-at Fault Model

 Only One line is faulty
 Faulty line permanently set to 0 or 1
 Fault can be at an input or output of a gate
Why Single Stuck-at Fault Model ?

 Complexity is greatly reduced

 Many different physical defects may be modeled by the same logical single
stuck-at fault
 Stuck-at fault is technology independent
 Can be applied to TTL, ECL, CMOS, BiCMOS etc.
 Design style independent
 Detection capability of un-modeled defects
 Empirically many defects accidentally detected by test derived based on
single stuck-at fault
 Cover a large percentage of multiple stuck-at faults
Multiple Stuck-At Faults

 Several stuck-at faults occur at the same time

 Important in high density circuits
 For a circuit with k lines
 There are 2k single stuck-at faults
 There are 3k-1multiple stuck-at faults
 A line could be stuck-at-0, stuck-at-1, or fault-free
 One out of 3k resulting circuits is fault-free
Multiple Stuck Fault Model (Contn’d)

 Intuitively, it seems that detecting all SSFs is sufficient to detect the MSFs.

Test that detects C SA0 is abc = 011

Current based fault Model (IDDQ Measurement)


 Subthreshold Conduction

 The transistor is partially conducting for voltages below the threshold

voltages. The region is referred to as weak-inversion
 Subthreshold Conduction

 This increases the mean and variance of IDDQ

Conceptionally simple:
 Apply the test pattern and wait for the transients to settle
 Compare the static current against a threshold
Fault Detection

 requires a test that creates a conducting path between VDD and GND

VDD pin

 A stuck or IDDQ test requires AB=11 in order

to provoke the short

 Remember, Observation is easy for IDDQ since

no propagation required

 These patterns are called pseudo-stuck-at patterns

Inverter With Defect Graphical Representation

 Design Rules to make design suitable for IDDQ Testing Click For Details
 The circuit should be properly initialized. This can be done by a set/reset signal or
through scan operation
 All static current dissipating logic should be switched off, this includes memory sense-
amps, dynamic logic, asynchronous logic, pull-up/pull-down resistors, special I/O buffers
and analog circuitry
 The circuit should be stable at the strobe point; there should be no pending events
 All inputs and bi-directional pins should be either at 0 or at 1
 If an input, output or bi-directional pin is pulled-up, it should be at logic 1 connected to
Vdd through an on pMOS; if pulled down then it should be at logic 0 connected to Gnd
through an on nMOS
 Special circuit structures should be avoided. If unavoidable, a mechanism should be
provided to switch-off these structures during Iddq testing. The examples of such
structures are gate and drain/source of a transistor be driven by the same transistor
group; feedback and control loops within one transistor group Back
IDDQ Test Measurement Strategies

Before IDDQ tests can be implemented on ATE, a threshold pass/fail reference value must be set

This represents the quiescent IDD value for the device

Off-Chip Current Monitoring Method

 Slow test times are a real disadvantage to IDDQ test strategy
 Some test methods have devised IDDQ measuring and threshold detecting hardware
 These hardware implementation consists of differential amplifier with threshold ref. Ckt., all of which
are mounted on the tester’s load board.

Test setup for off-chip current monitoring method

On-Chip Current Monitoring Method

 To avoid delay due to measurement equipment

 To avoid LRC drop across the current probe to avoid
 To avoid mechanical limitations of commercially available current probes
 Not used frequently

Test setup for on-chip current monitoring method

 Advantages

 Covers most bridge faults

 Covers some open faults
 Higher defect coverage than stuck-at tests

 Disadvantages

 Circuit must be designed with low IDDQ

 Test application slow
 Some open faults escape IDDQ tests
 Some timing faults escape IDDQ tests
 Current threshold has to be empirically established
Delay Faults

 Transition faults and Gate Delay faults

 Models slow-to-rise or slow-to-fall transition on logic gate

 Path Delay Faults

 Models slow-to-rise or slow-to-fall transition on some path(s) from primary input to
primary outputs

 Advantage: Covers transition and gate delay faults

 Disadvantages: Test application in non-scan sequential circuits can not be done at-
speed. Number of paths may be (exponentially) large
Major Delay Fault Types

Three Types
 Path delay fault (can be distributed timing failure)
 Delay of at least one sensitizable path exceeds specified clock cycle time
 Associated with a Path (e.g. A-B-C-Z)
 More complicated than gate-delay fault
 Number of paths grows exponentially
 Gate delay fault (local timing failure)
 Delay of at least one path through the faulty gate exceed specified cycle time
 Transition Delay fault (local timing failure)
 Delay of all paths through faulty gate exceed specified cycle time

 Two Types
 Slow-to-rise (STR) and Slow-to-Fall (STF)
 Example: six faults in AND
 A slow-to-rise, A slow-to-fall C
 B slow-to-rise, B slow-to-fall
 C slow-to-rise, C slow-to-fall
 Two pattern test required
 First pattern P1 initialize a net
 Second pattern P2 detects stuck-at fault at net
 TF very popular delay fault model
 Transition fault ATPG similar to stuck-at ATPG
Transition Delay Fault Model

 Two Types

 Slow-to-rise (STR) and Slow-to-Fall (STF)

 Example: six faults in AND

 A slow-to-rise, A slow-to-fall
 B slow-to-rise, B slow-to-fall C
 C slow-to-rise, C slow-to-fall
 Two pattern test
 First pattern P1 initialize a net
 Second pattern P2 detects stuck-at fault at net

 TF very popular delay fault model

 Transition fault ATPG similar to stuck-at ATPG
Transition Delay Fault Model (Cont’d..)

Delay Fault Requires Two-pattern Test

 Two patterns
 Initialization pattern (P1): place initial value at fault site
 Propagation pattern (P2): place the final value and propagate to the
observable output
 As opposed to SSF
 Only one pattern required
Transition Delay Test
Two Methods of Transition Delay Test

 Launch on Capture (LOC)

 Launch on Shift (LOC)

 Scan Enable signal has to distinguish the features of both the method

Waveform for LOS and LOC delay test

Comparison of both the methods

Launch-on-Capture (LOC) Launch-on-shift (LOS)

1) No constraints for scan 1) High Fault Coverage

Advantages enable signal 2) Compact test patterns
3) Combinational ATPG
Disadvantages 1) Medium Fault Coverage 1) Implementation of fastscan
2) More test pattern needed 2) Enable signal needed
3) Sequential ATPG
Bridging Faults

 Unintended short between two signal and creates wired logic

 Shorts within logic gate are not bridging faults
Fault Activation & Propagation

A fault can be detected if it is activated and propagated

 Fault activation create different values (w.r.t. to faulty and fault free circuits) at the
fault site
 Fault propagation (sensitized) to a primary output
 line e is sensitized to output if output value changes when line e changes
 A path composed of sensitized lines is called a sensitized path

Refer Figure of next page

 e stuck-at 0 is activated because c=1,
 good e=1; faulty e=0
 e stuck-at 0 fault is propagated to output f
 e and f are sensitized
 path e-f is a sensitized path
 So, e stuck-at 0 is detected
Common ATPG Terminology

 Fault Equivalence
 Fault Dominance
 Fault Collapsing
 Fault Grading (Vector Grading)
 Fault Masking
Fault Equivalence

 Equivalent Faults

 Two faults, A & B are said to be equivalent in a circuit , if the function under A is
equal to the function under B for any input combination (sequence) of the circuit
 No test can distinguish between A and B
 In other words, test-set(A) = test-set(B)
Fault Equivalence (Cont’d..)

 AND gate
 all s-a-0 faults are equivalent
 OR gate
 all s-a-1 faults are equivalent
 NAND gate
 all the input s-a-0 faults and the output s-a-1 faults
are equivalent
 NOR gate
 all input s-a-1 faults and the output s-a-0 faults are
 Inverter
 input s-a-1 and output s-a-0 are equivalent
 input s-a-0 and output s-a-1are equiv
Fault Dominance

 Dominance Relation
 A fault B is said to dominate another fault
 Α in an irredundant circuit, if every test (sequence) for A is also a test (sequence)
for B I.e., test-set(B) > test-set(A)
 No need to consider fault B for fault detection

Test (A) Test (B) A is dominated by B

Fault Dominance (Cont’d..)

 AND gate
 Output s-a-1 dominates any input s-a-1
 NAND gate
 Output s-a-0 dominates any input s-a-1
 OR gate
 Output s-a-0 dominates any input s-a-0
 NOR gate
 Output s-a-1 dominates any input s-a-0
Fault Collapsing

 Reducing the set of faults to test for by using equivalence classes is called fault
 If a set of faults is functionally equivalent, we only need to use one test to detect any
single one of them
 Note that a test that detects functionally equivalent faults cannot diagnose which fault
is present
 Simple example: 2-input NAND gate
Input stuck-at-0 is equivalent to output stuck-at-1  collapse !!
Fault Grading

 The act of simulating a target vector against a good circuit description and a circuit
description that contains a fault

 The goal being to see if the expected response is different between the two circuits at
an observe point

 If a difference is detected, then the fault has been detected

 If a difference is not detected, then the fault is masked for that vector (not detected)
Fault Masking

 The fault that is not able to be detected due to a circuit configuration problem such as

 An exercised fault can not be driven uniquely to an observe point

 This kind of faults needs to be masked

ATPG (Automatic Test Pattern Generation )
Why ATPG ?

 Test generation can be the longest phase of the design cycle if done manually

 Functional verification will not give high stuck-at-fault coverage

 ASICs made with a synthesis tool are especially hard for manual test
generation, because human insight is missing in a machine generated netlist
ATPG consists of two main steps

 Generating patterns
 Performing fault simulation to determine which faults the patterns detect
Concepts for Automatic Test Pattern Generation

 Fault activation
 Setting the faulty signal to either 0 or 1 is a Line Justification problem
 Fault propagation
 select a path to a PO  decisions
 Once the path is selected  set of line justification (LJ) problems are to be
 Line Justification
 Involves decisions or implications
 Incorrect decisions: need backtracking
Fault Classes

There are mainly two fault classes

 Testable (TE)

 Untestable (UT)
Testable Faults

 Faults that cannot be proven untestable

 Subcategorized as:

 Detected (DT)
 DET_Simulation (DS)
 DET_Implication (DI) Click For Details
 POSDET_Untestable (PU)
 POSDET_Testable (PT) Click For Details
 ATPG_Untestable (AU) Click For Details
 UNDetected (UD)
 UNControlled (UC)
 UNObserved (UO) Click For Details
Detected (DT)

 The detected fault class includes all faults that the ATPG process identifies as
 The detected fault class contains two subclasses

 DET_Simulation (DS) - faults detected when the tool performs fault simulation
 DET_Implication (DI) - faults detected when the tool performs learning analysis

Posdet (PD)

 The posdet, or possible-detected, fault class includes all faults that fault simulation
identifies as possible-detected but not hard detected
 A possible-detected fault results from a 0-X or 1-X difference at an observation
 The posdet class contains two subclasses

 POSDET_Testable (PT) - Potentially detectable posdet faults PT faults result when

the tool cannot prove the 0-X or 1-X difference is the
only possible outcome. A higher abort limit may reduce
the number of these faults

 POSDET_Untestable (PU) - Proven ATPG_untestable and hard undetectable

posdet faults
ATPG_Untestable (AU)

 The ATPG_untestable fault class includes all faults for which the test generator is
unable to find a pattern to create a test, and yet cannot prove the fault redundant

 Testable faults become ATPG_untestable faults because of constraints, or

limitations, placed on the ATPG tool (such as a pin constraint or an insufficient
sequential depth)

 These faults may be possible-detectable, or detectable, if you remove some

constraint, or change some limitation, on the test generator (such as removing a pin
constraint or changing the sequential depth)

Undetected (UD)

 The undetected fault class includes undetected faults that cannot be proven
untestable or ATPG_untestable
 The undetected class contains two subclasses:

 Uncontrolled (UC) - Undetected faults, which during pattern simulation, never

achieve the value at the point of the fault required for fault
detection—that is, they are uncontrollable

 Unobserved (UO) - Faults whose effects do not propagate to an observable point

 All testable faults prior to ATPG are put in the UC category. Faults that remain UC
or UO after ATPG are aborted, which means that a higher abort limit may reduce
the number of UC or UO faults.
Untestable Faults

 Faults for which no pattern can exist to either detect or possible detect them

 Cannot cause functional failures, so the tools exclude them when calculating test

 Subcategorized as

 Unused (UU) Click For Details

 Tied (TI) Click For Details

 Blocked (BL) Click For Details

 Redundant (RE) Click For Details

Unused (UU)

 The unused fault class includes all faults on circuitry unconnected to any circuit
observation point.

Example of “Unused” Fault in Circuitry

Tied (TI)
 The tied fault class includes faults on gates where the point of the fault is tied to a
value identical to the fault stuck value. The tied circuitry could be due to:
 Tied signals
 AND and OR gates with complementary inputs
 Exclusive-OR gates with common inputs

Example of “Tied” Fault in Circuitry Back

Blocked (BL)
 The blocked fault class includes faults on circuitry for which tied logic blocks all
paths to an observable point
 The tied circuitry could be due to
 Tied signals
 AND and OR gates with complementary inputs
 Exclusive-OR gates with common inputs

Example of “Blocked” Fault in Circuitry
Redundant (RE)

 The redundant fault class includes faults the test generator considers undetectable.
After the test pattern generator exhausts all patterns, it performs a special analysis to
verify that the fault is undetectable under any conditions.

 In this circuit, signal G always has the value of 1, no matter what the values of A, B,
and C. If D is stuck at 1, this fault is undetectable because the value of G can never
change,regardless of the value at D
Automatic Test Pattern Generation (ATPG) Methods

 Based on Truth Table

 Based on Boolean Equation
 Based on Structural Analysis
 D-algorithm
 9-Valued D-algorithm
 PODEM [ Path Oriented Decision Making ]
 FAN [ Fanout Oriented]
Typical sequence involved in processing/generating a single scan test

1. Set up the scan chain configuration.

2. Shift values into the active scan chains.
3. Exit the scan configuration.
4. Apply stimulus to the test circuit inputs and measure the outputs.
5. Pulse clocks to capture the test circuit response in flip-flops.
6. Set up the scan chain configuration.
7. Shift values out of the active scan chains.
8. Exit the scan configuration.
A Scan Sequence

Scan Clock

Scan input

Scan Enable

Scan Output

BIST (Built-In Self Test)
There are generally two types of BIST methods:

 MBIST (Memory Built-In Self Test)

 LBIST (Logic Built-In Self Test)

 A memory is considered embedded if some or all of its terminal are not directly
connected to the pins of the host chip.
Difficulties in testing embedded memories:

 The amount of extra interconnect needed

 Resulting interconnect may lead to large and probably uneven propagation delay
making application of test pattern difficult at-speed

 The number of memory inputs and outputs might be more than number is chip-level
signal pins
What is MBIST ?

 Memory Built-in self-test (MBIST) circuitry, along with scan circuitry, greatly
enhances a design’s testability. BIST leaves the job of testing up to the device itself,
with minimum direct interaction from external tester

 The principle is to generate test vectors, apply them to the circuit under test ( CUT )
and then check/compare the response

 Reduces the routing of signals needed at the chip level

 Embedded memories can be tested with ease
 Reduces test application time and simplifies pattern generation
 Reduces amount of test data to store since on chip circuitry generates test
 Facilitates hierarchical test capabilities -- lets you easily test model, block,
design, and system levels
 BIST controller can be shared across memories
 Lower cost of test and better fault coverage

 Chip area overhead for:

 Test controller
 Hardware pattern generator
 Hardware response compactor
 Testing of BIST hardware
 Pin overhead – At least 1 pin needed.
 Performance overhead – extra path delays.
 Yield loss – due to increased chip area.
 Increased BIST hardware complexity – especially when BIST hardware should
also be testable.
MBIST Controller

MBIST Architectural View

MBIST Controller consists of

 A signal generation block (Signal Gen) contains circuitry to produce the

address, data and control values needed to create each test pattern

 A comparator(Comp) compares the values read out of the memory with expected
values generated by the signal generation block

 A finite state machine(FSM) is used to control the overall sequence of events.

For more details of each segment, Click Me

 A signal generation block (Signal Gen) contains circuitry to produce the
address, data and control values needed to create each test pattern that is to be
applied to the memory. This block typically contains an up/down counter to generate
address sequences needed by most memory test algorithms

 A comparator(Comp) compares the values read out of the memory with

expected values generated by the signal generation block. The result of each
comparison is accumulated into a status flip flop in order to provide a go/no go result
at the end of test

 A finite state machine(FSM) is used to control the overall sequence of events.

I.e, it determines if the address counter should be counting up or down or if data
being generated should be a marching 0 or marching 1 pattern


 System addresses (sys_addr) — The system address inputs to the memory array

 System data inputs (sys_di) —The system data inputs to the memory array

 System write enables (sys_wen) —The system write enable which enables R/W operation

 Reset (rst_l) — An active-low signal that resets the finite state machine.

 Clock (clk) — The clock for the MBIST controller.

 Hold (hold_l) — An optional active-low signal that forces the MBIST controller to stop processing and
maintain its current state.

 Test (test_h) — An active-high signal that enables the MBIST controller. When test_h is high, self-test
is in progress. When test_h is low, the hold_l signal is activated to discontinue the clocking of the BIST
controller and conserve power

 Diagnostic Mode (debugz) — (Debug only) The diagnostic mode enable signal. When debugz is low,
the BIST controller performs the default memory tests. When debugz is high, the diagnostic mode is
enabled. Works with hold_l and scan_out.

 Write enable (wen) —The output that drives the write enable of the one or more
memories under test
 Restart (restart_h) —An active high signal that is asserted when the BIST controller is in a
restart mode, and is deasserted when the controller successfully restarts
the BIST
 Test Done (tst_done) —When high, indicates completion of the self-test operation.
 Fail (fail_h) —The pass/fail flag for the BIST controller.
 Data Outputs (di_n) —The memory data inputs.
 Address Outputs (ao_n) —The memory address inputs.
 Scan Output (scan_out) —(Debug only) The scan output port for diagnosing serially
scanned out failing data.
 Compress (compress_h) —(Compressor only) An active-high signal that controls
compressor operation. When high, it enables data compression.
BIST Controller with Comparator
BIST Controller with compressor
Comparator Vs Compressor

Comparator :
 Used for testing RAMs
 Stops on the first fail
 Adds diagnosis capabilities to the BIST controller
 However it adds additional area overhead since comparator width is same as
memory data width

Compressor :
 Used for testing ROMs – since we need to compress only once and a golden
signature is used
 A ROM test requires it since here the repair feature is not needed
Basic Fault Types (Memory BIST)
 Stuck-at
 Transition
 Coupling
 Neighborhood Pattern Sensitive
 Address Decoder Faults (ADF)
 Retention Faults (RF)
 Stuck-at faults

A memory fails if one of its control signals or memory cells remains stuck at a particular
values(0 or 1)

Stuck-at state diagram

 Transition faults

A memory fails if one of its control signals or memory cells can not make a transition
from 0 to 1 or vice versa.

Transition fault state diagram

Transition fault state diagram

 Coupling faults

Memories can also fail when a write operation in one cell influences the value in
another cell.

Coupling faults falls into several categories:

> Inversion
> Idempotent
> Bridging
> State
 Inversion Coupling faults

Commonly referred to as CFins, occurs when one cell’s transition causes inversion in
another cell’s value

 Idempotent Coupling Faults

Commonly referred to as CFids, occurs when one cell’s transition forces a particular
value in another cell

 State Coupling Faults

Abbreviated as SCFs,when a certain state in one cell causes a specific state in another
 Bridge Coupling Faults

Abbreviated as BFs, when a short or bridge exists between two or more cells or

AND Bridging fault (ABF)

> ABFs exhibits AND gate behavior, bridge has 1 value only when
all connected cells or signals have a 1 value

OR Bridging fault (OBF)

> OBFs exhibits OR gate behavior, bridge has 1 value when any of
the connected cells or signal have 1 value
 Neighborhood Pattern Sensitive Faults

Memory cell can fail when write operation on a group of surrounding cells that affects
the values of one or more neighboring cells.
 Address Decoder Faults

No cell will be accessed with certain address, or multiple cells are accessed
simultaneously, or a certain cell can be accessed with multiple addresses

 Retention Faults

A cell fails to retain its logic value after some time

Memory BIST algorithms

 Need of algorithms

 Certain types of pattern sequences need to be applied to exercise and detect the
different failure modes
 Needs to detect as many as faults classes in least number of operations
(Conserving test time)
Different types of Algorithms (MBIST)

 ATS(Algorithm Test Sequence) and Modified ATS (MATS)

 Provides shortest march test sequence for stuck-at faults
 March
 Most common algorithm
 Data will march in and out to memory location and thus pattern formed
 Derivatives : March A, March B, March C
 Unique address
 checkerboard
March C algorithm in Detail
 Algorithm consists of following Steps:

 Write 0s to all locations starting at the lowest address (initialization).

 Read 0 at lowest address, write 1 at lowest address, repeating this series of
operations until reaching the highest address.
 Read 1 at lowest address, write 0 at lowest address, repeating this series of
operations until reaching the highest address.
 Read 0 from the lowest address to the highest address.
 Read 0 at highest address, write 1 at highest address, repeating this series of
operations until reaching the lowest address.
 Read 1 at highest address, write 0 at highest address, repeating this series of
operations until reaching the lowest address.
March C algorithm in Detail (Cont’d..)

 Consists of 11 operations, writes and reads words of 0s, followed by writing/reading of

words of 1, in both descending and ascending address space.
 Also known as March 11n where 11n is the number of operations per memory word.


March C+ (March 13n) algorithm

March C+ (March 14n) algorithm

March C+ detects same faults as
March C, in addition to that stuck-
Open faults, and some timing faults
 March algorithm normally reads and writes words of either all 1’s or 0’s.By varying
the data values or data background fault detection can be increased.

Example : 4x4 RAM with data background Click for Details

The March2 algorithm with a varied background becomes

 Write 0101 to all locations starting at address 0 up to address 3

 Read 0101 at address 0, write 1010 at address 0, read 1010 at address 0, repeating
this series of operations in addresses 1, 2, and 3
 Read 1010 at address 0, write 0101 at address 0, read 0101 at address 0, repeating
this series of operations in addresses 1, 2, and 3
 Repeat steps 2 and 3, but this time begin at address 3 working down to address 0

Checkerboard Algorithm

 The checkerboard algorithm detects stuck-at faults for memory cells and adjacent
cell shorts, providing previous tests prove the address decoding circuitry is fault free

Diagonal Algorithm

 The diagonal algorithm detects stuck-at faults in some memory cells, as well as
faults on address lines.
MBIST Controller Modes

 Functional Mode
This is the normal functional mode in which all the memories are connected to
Functional I/Os, and MBIST Controllers are idle.

 Go/no-go Test Mode

In this mode MBIST Controllers provide test inputs to Memories and captures output
and compare it with expected data at-speed.

 Debug Mode
In this mode Controllers check memories for failure and scans out the failed data to the
tester. Fail data scan out takes place with slow tester clock

 Retention Mode
A test which tests the memory’s capability to retain the data contents.
MBIST Diagnostics using DATA logger


Failure Hold_ctlr

Monitor Restart

Data Logger


DATA Logger (Contd..)

 By default , the go/no go test will indicate failures to ensure that the bad part is
rejected . It is necessary to identify the cause of these failures . Data needed to
evaluate the cause of this failure is provided by Data Logger

 Data Logger requires the controller’s hold capability as well as additional functionality
to down load the failing data on every occurrence of a miscompares

Click here for operation details of Data Logger

 BIST Controller restarts the algorithm from start if a defect is encountered. Error
detection is disabled until all the data is flushed .The restart happens immediately
after the data from pending failures is processed .The sequence is as follows :
1. A failure is first detected in the controller .
2. In case of diagnostics with hold , the BIST controller is stopped immly. In case of
diagnostics with no-hold , the BIST Controller continues.
3. For diagnostics with hold, the controller is stopped until the diagnostics data is
completely scanned out. The restart is then initiated .
4. For diagnostics with no hold , if the info of the 1st failure is completely shifted out
before a 2nd failure , controller continues its normal operation. However if the 2nd
failure occurs before the 1st failure is scanned out the controller is stopped and the
diagnostic info of the 1st and 2nd failure is scanned out before restarting the controller.
5. When the point where the controller was stopped is reached , normal BIST operation
resumes to detect further failures .
Top Level BIST Signals

Port IO Function


I BIST diagnostic clock

BIST_RST_L I Reset to BIST logic, active low

BISTMODE I Enable BIST, active high

I BIST Controller select

I MBIST diagnostic mode active when LOW, normal BIST mode when HIGH.

BIST_RESUME I Resume MBIST operation from retention state.

FAIL_L O Indicates BIST test has failure when LOW, passing when HIGH.

BIST_DONE O Active when MBIST test is complete, active high

O Scan output for Diagnostic Mode failure data.

BIST_RETENTION O BIST operation is idling in a retention mode when HIGH.

What is Logic BIST ?

 Form of testing for logic circuits where the stimulus generator and/or the response
verifier is placed within the circuit. The most common form of logic BIST is to use
linear feedback shift registers (LFSR) to conduct pseudo-random pattern
generation (PRPG) and to conduct output pattern compression (signature analysis)
using MISR (Multiple Input Shift Register)

 Logic BIST architecture is called STUMPS (Self-Test Using MISR Parallel Shift
Register ) architecture where scan chains configured in the designs are called
STUMPS channels
Phase Shifter (XOR Gates)

Compactor (XOR Gates)

Logic BIST Block Diagram

PseudoRandom TPG and LFSRs(Linear Feedback Shift Register)
 PseudoRandom (PR) implies random patterns without repetition.
For (a), the parity of the feedback tabs defines the input, Y0.

Let y0, y1, y2 represent the present state of the registers and Y1,Y2,Y3 represent the
next state, then Y1 = y0, Y2 = y1 and Y3 = y2.

 The leftmost (a) LFSR was arbitrarily initialized to 001.

 Generating 000 is not possible (the last row is identical to the first row).
 The maximal cycle of the LFSR is 7: (23 - 1)
LFSRs (Linear Feedback Shift Register)
 Example (c) has 3 feedback tabs but can only generate 4 patterns.
 Adding a NOR as shown allows the all-zero pattern.

Assume start state is:

LFSR Configurations

Two configurations:


LFSR Configuration Examples
 This LFSR is equivalent to the version given in (a) previously.

Modular version

 LFSRs that implements polynomial 1 + X3 + X4.


Response Compaction

 The response of the logic-under-test needs to be checked after test application

with an LFSR.
 It is difficult to check the response of every pattern (storage requirements).
Instead, the responses are compressed and the compressed response is checked
 The probability of aliasing decreases as the length of the test increases
 LBIST circuitry calculates a test signature from the circuit under test by using a
multiple input shift register, or MISR. Like a PRPG, a MISR is an LFSR
 MISR takes output values from the circuit and produces a compacted output
pattern or test signature.
Signature Analysis
The signature is just the remainder of the division of the response by the characteristic
polynomial of the LFSR, P(X).
For example, assume M(t) = {10110001} is applied to either in state (000):
CUT with LFSR and MISR

Output Sequences Signature Analyzer

Output Sequences
Boundary Scan ( IEEE 1149.1 or JTAG )

 Testing Printed Circuit Boards (PCBs) with Bed-of- nails tester is no longer
possible due to :

 Multi-layer PCBs
 Reduced spacing between wires
 Increasing the complexities of logic

 Due to physical space constraints and loss of physical access to fine pitch
components fixturing cost increased dramatically while fixture reliability decreased
at the same time
Purpose of the Standard

 A standard interface is needed to integrate components from different vendors

 A serial interface is provided to serially feed test instructions and test data
into the component
 Lets PCB wires be tested separately from components
 Allows reading out the test results
 Allows testing of multiple chips on board in sequence
 Allows activation of internal Built-In Self-Test (BIST)
What is boundary Scan ?

 Boundary-scan, as defined by the IEEE Std. 1149.1 standard, is an integrated

method for testing interconnects on printed circuit boards that is implemented at the
IC level.

 Provides a means to test interconnects between integrated circuits on a board without

using physical test probes

 Useful for both board test and core test

Principle of Boundary Scan

Each boundary-scan cell can:

• Capture data on its parallel input PI

• Update data onto its parallel output PO
• Serially scan data from SO to its neighbor's SI
• Behave transparently: PI passes to PO
Note: all digital logic is contained inside the boundary-scan register
Boundary Scan Chip Architecture
TAP Signals
Test Data In(TDI)
:Serial data in
:Sampled on rising edge
:Default = 1
Test Data Out (TDO)
:Serial data out
:Sampled on falling edge
:Default = Z (only active during a shift
Test Mode Select (TMS)
:Input Control
:Sampled on rising edge
:Default = 1
Test Clock(TCK)
:Dedicated clock
:Any frequency
Test Reset (TRST*)
:Async reset
:Active low
:Default = 1
Basic Boundary Scan Cell

 Four mode of operations : Normal, Capture ,Shift, Update

 All Boundary Scan cells are combined in a shift register with parallel inputs and
outputs and generate the serial scan path.
TAP(Test Access Port) Controller
TAP Controller State Diagram
Standard Resisters
Instructions Summary
Sample and Preload Instruction

 Boundary scan register selected

 The instruction sets up the

boundary-scan cells either to
sample (capture) values or to
preload known values into the
boundary-scan cells prior to some
follow-on operation.

 Device in functional Mode, not in

test mode

 Mandatory Instruction
Bypass Instruction

 1-bit Bypass register selected

 Used to allow quick passage

through this device to another
device connected in the chain

 Device remains in normal

functional mode

 Bypass register, when used will

be placed between TDI and TDO

 Mandatory Instruction
Extest Instruction

 Boundary-scan register selected

 Used to apply patterns to the inter-

connect structures on the board

 Boundary-scan cells have permission

to write to their outputs (device in test

The code for Extest used to be defined

to be the all-0s code.

 Mandatory Instruction
Intest Instruction

 Boundary scan register selected

 Used to apply patterns to the device

itself (Internal logic of the device)

 Boundary scan cells have permission

to write to their outputs (device in
test mode)

 One of the optional instructions,

which do not needs to be impleme-
nted but it has prescribed operation
if they are implemented
Idcode Instruction

 Used to select the Identification register

between TDI and TDO, preparatory to
loading the internally held 32-bit
identification code and reading it out
through TDO.

 The 32 bits are used to identify the

manufacturer of the device, its part
number and its version number

 Optional Instruction
Usercode Instruction

 Use to capture an alternative 32 bit

identification code for dual personality
devices e.g, FPGA, PLD

 Usercode selects the same 32-bit

register as Idcode, but allows an altern-
ative 32 bits of identity data to be
loaded and serially shifted out

 Optional Instruction
RunBist Instruction

 Control registers for initiating internal

BIST (Memory or Logic)

 Pass/fail register targeted as final


 The self-test routine must be self-

initializing (i.e., no external seed
values are allowed), and the
execution of RunBist essentially
targets a self-test result register
between TDI and TDO.

 At the end of the self-test cycle, the

targeted data register holds the
Pass/Fail result.

 Important optional instruction

Clamp Instruction

 Known values are pre-loaded into

boundary scan cells using Preload

 Clamp drives these values to the out-

put pins but leaves Bypass register as
the selected register

 Clamp would be used to set up safe

guarding values on the outputs of
certain devices in order to avoid bus
contention problems
HighZ Instruction

 Control-to-Z values are pre-loaded

into high-Z control cells using the
Preload instruction

 HighZ drives these values to the

three-state controls causing them
to go to their high-Z drive state but
leaves Bypass register as the
selected register between TDI and

 HighZ is similar to Clamp, but it

leaves the device output pins in a
high-impedance state rather than
drive fixed logic-1 or logic-0 values
Instructions Summary
Insturctions : Mandatory / Optional ?

SAMPLE / PRELOAD  Mandatory

EXTEST  Mandatory
BYPASS  Mandatory
CLAMP  Optional
USERCODE  Optional
IDCODE  Optional
RUNBIST  Optional
INTEST  Optional
HIGHZ  Optional
Bypass, Identification and boundary scan registers
The Bypass register

 One-bit shift register, selected by the Bypass instruction and provides basic serial-
shift function

 Captures a hard-wired 0

 Note: in the Test-Logic/Reset state, the Bypass register is the default register if no
identification register presents

Typical Design of 1-bit bypass register

Identification Register
 32-bit shift register
 Selected by Idcode and Usercode instruction
 No parallel output
 Captures a hard-wired 32-bit word
 LSB = always logic 1(To distinguish between ID register and bypass reg.)
 1-11 = manufacturer code
 12-27 = part code
 28-31 = version code
 Main function: identify device owner and part number
 Note: Id code is power-up instruction if Identification Register is present, else Bypass
Register will be considered
 Any operation of the device identification register has no effect on the operation of
the system logic
The Boundary-Scan Register
 Shift register with boundary-scan cells on:

 Device input pins

 Device output pins
 Control of three-state outputs
 Control of bidirectional cells

 Selected by the Extest,Intest, Preload and Sample instructions

Standard Resisters
Application at the Board Level

General Strategy
Boundary Scan Description Language (BSDL)
Purpose: Facilitate communication of information describing test logic (interface with
CAD tools)

 Mainly used by ATPGs and synthesis tools

BSDL : Features

 Allows the specification of ...

 Length of boundary scan register

 Availability of reset (TRST) pin
 Physical location of TAP pins
 Instruction codes
 Device identification code

 Does not allow the specification of ...

 TAP controller state diagram

 Availability of bypass register
 Length of Device Identification Register
 Availability of mandatory instructions
Questions ..??
Questions ???
Thank You..