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Illinois Scan Architecture

Janak H. Patel
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
jhpatel@illinois.edu
Cost of a Chip
 300mm wafer will give 700 ~1cm2 chips
 Material Costs (wafer, copper etc) ~5%
 Fab amortization cost ($3B/fab) plus
Fab operational cost ~25%
 Personnel cost ~20%
 Package Cost ~10%

 Testing Cost ~40% !!!


Semiconductor Wafer
Manufacturing test is done
at wafer level without cutting
out the chips.

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Cost of Testing Semiconductor Chips
 Three main variable components
 Test Application Time
 When amortizing the cost of a tester over all chips,
higher test time results in to higher actual cost
 Rule of thumb: 1 second per chip!

 Test Data Volume


 Low and medium cost testers have limited storage

 Tester Pins
 Cost of a tester is directly proportional to the number
of pins it supports

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Example: An IBM chip
 7million gates (logic only, RAM not included)
 250k Flip-Flops
 Full Scan design, all FFs connected as shift
register
Scan Scan
250,000 ffs
in out
 7000 Test Vectors
 Test Application Time: 7000x250k = 1.75G cycles
 at 100MHz scan speed it takes 17.5 Seconds!
 at 500MHz scan speed it takes 3.5 Seconds
 Tester memory required: 7000x250k = 1.75G bits
 Test Responses require additional 1.75G bits 4
Parallel Scan
1000 Parallel Scan Chains by 250 FFs

Scan-in Scan-out

1000 1000
scan-in pins! scan-out pins!

Reduces Test Vector Load time by a factor of 1000!

Scan Channels on most Testers range from 10 to 200 5


Parallel Scan Output Compaction
100 Parallel Scan Chains by 2500 FFs output
compactor

Scan-in

A Combinational Compactor is a tree of XOR gates

A Sequential Compactor is a Linear Feedback Shift Register with


multiple parallel inputs XORed. Also called a Multiple Input
Signature Analyzer (MISR) 6
Parallel Scan - Summary
 Scan loading time can be reduced by dividing the
single scan chain in to parallel scan chains

 Some Observations
 Output Compaction is well established
 Number of scan chains is limited by the availability
of pins on a chip and tester scan channels
 Additional “pins” on an embedded core require
more routing in the SOC
Parallel Scan has no impact on test data volume

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Test Vector Compaction
 For example, all 40 ISCAS 85 and
ISCAS89 (full scan) circuits, sizes Test Vectors
of the test sets generated by Lower Min
Circuit
Bound Test
MinTest (Hamzaoglu and Patel, ICCAD
C432 27 27
1998, pp. 283-289) meets Lower
C5315 37 37
bounds for 31 out of 40 ISCAS
C7552 65 73
circuits.
S1196 113 113
 This shows that Compaction
S1423 20 20
has already reached theoretical
S5378 97 97
lower bounds in many
S38714 62 68
instances
 Need solutions beyond vector
compaction
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BIST: STUMPS Architecture
P. H. Bardell and W. H. McAnney, “Self-Testing of Multichip Logic Modules,”
Proc. Of Int. Test Conf., pp. 200-204, Nov. 1982. (used by IBM for multi-chip-modules)

Scan Chain
LFSR

MISR
Scan Chain

Scan Chain

Scan Chain

Linear Multiple
Feedback Phase
Circuit Under Test Input
Shift Shifter Signature
Register Register
This has the same limitations as any other BIST based scheme
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Limitations of Logic BIST
 BIST is excellent for Data Volume Reduction, But
 Lower Fault Coverage. Test Point insertion and/or
additional logic in test generator is required to
cover Random Resistant Faults
 Design Modification needed to permit any arbitrary
test pattern
 Tri-State logic must be fully decoded
 No floating bus is permitted, since unknown values
can corrupt the signature
 Switching activities of various modules, and hence
the power, cannot be easily controlled
 Will almost always increase the tester time!
 Failure Diagnosis becomes extremely difficult
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Proposed New Method
 Illinois Scan Architecture
 Applicable to full-scan embedded cores and full-
scan stand-alone chips
 Addresses all issues raised earlier –
Low test application time, low pin overhead, and
low test data volume
 Does not have any of the limitations of the BIST
 No test point insertions and No design
modifications!
 Undesirable test vectors can be filtered, e.g.,
Vectors that produce Tri-State Conflicts, Unknown
value generation, or High switching activity
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Illinois Scan Architecture

Take a Serial Scan


Scan Scan
in out

1. Divide it up into several chains


keeping the same Scan-in pin
2. Add a MISR to compact the outputs
Scan Scan
in out

MISR
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Illinois Scan
Internal Scan Chains

Output Compactor
Scan-in
pin

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Untestable Faults in Illinois Scan
 In the figure shown on left,
1
0 all three scan chains will
have identical test vectors
scan in
1
0  Therefore, only applicable
test vectors are 000 and
1
0 111 for the AND gate
 Test vectors 110, 011 and
101 cannot be applied due
to Broadcast constraint
 This makes three faults on
the AND gate Untestable

In practice, how serious is this problem?


How many faults become untestable?
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Additional Untestable Faults
 Illinois Scan puts constraints
on inputs 1200

 Cannot generate tests for 1000

Untestable Faults
some of the faults that 800
are testable
600
 The number of such
“Additional Untestable 400
Faults” is surprisingly 200
small
0
 Experimental Data for

ILS-13207

ILS-15850

ILS-35932

ILS-38417

ILS-38584
Scan Chain divided into 16
chains (arbitrary partition),
with a single scan input.
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Two Test Modes of Illinois Scan
1. Broadcast Test Mode
2. Serial Test Mode
Scan Chain 1 Scan In
Scan Chain 1

MISR

MISR
Scan Chain 2 Scan Chain 2

Scan In •
• •
• •

Scan Chain n
Scan Out
Scan Out Scan Chain n

Mode 2 for covering the loss of


1. Reduces Scan Time by a factor of n
fault-coverage in the Broadcast Mode
2. Reduces Scan Data by a factor of n
Generates “top-off vectors”.
But may require many more vectors
Note: Most industrial circuits do
and may reduce fault-coverage!
not use Mode 2.
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Number of Test Vectors
400
scan vectors
350
300 broadcast vectors
Vectors

250
200
150
100
50
0
fs13207

fs15850

fs35932

fs38417

fs38584
ILS-13207

ILS-15850

ILS-35932

ILS-38417

ILS-38584
Circuit
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16
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Number of Test Cycles
200,000
175,000 scan cycles
150,000 broadcast cycles
125,000
100,000
Cycles

75,000
50,000
25,000
0
fs13207

ILS-13207

fs15850
ILS-15850

fs35932
ILS-35932

fs38417

ILS-38417

fs38584

ILS-38584
Circuit

Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16


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Illinois Scan Data Volume
450,000

400,000 Scan Test Data


350,000 Broadcast Test Data

300,000
Data Bits

250,000

200,000

150,000

100,000

50,000

0
ILS-arb

ILS-arb

ILS-arb

ILS-arb

ILS-arb
fs13207

fs15850

fs35932

fs38417

fs38584
Circuit
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16
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Illinois Scan
internal scan chains

scan-in
pin

output
compactor

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Illinois Scan with multiple pins
internal scan chains

external
scan-in
pins
output
compactor

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IBM Data using Illinois Scan (OPMISR+)

Gate Scan Test Time Test Volume


Design Count flip-flops Reduction Reduction

Chip1 1.7M 230k 130x 200x


Chip2 2.1M 31k 38x 54x
Chip3* 715k 41k 7x 21x
Chip4* 1.2M 65k 8x 12x

* These chips already had their scan divided by customer


“….scan fan-out, which is sometimes informally referred to as Illinois Scan [ix].
In the Cadence ATPG tools we refer to this as OPMISR+.”

Data and quote From: Test Compression Methods in Cadence Encounter Test Design Edition,
Technology Application Note, December 2003

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Intel Data on Illinois Scan
From a Paper by D. Wu et. al. of Intel, published in 2003 Int.
Test Conf.

“The first test chip has 81 scan-in and 81 scan-out channels, we


use Illinois Scan with 4 scan-in and 81 scan-out. The results are
quite surprising: both methods got the same test coverage.”

“We have implemented Illinois scan into one of the


microprocessors, but the silicon results will not be ready for the
timing of this year’s ITC.”

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More Data on Illinois Scan
7M Gates, 250k flip-flops, 7000 test vectors

Illinois
Scan

Source: V. Chickermane, B. Fautz and B. Keller,


Channel-Masking Synthesis for Efficient On-Chip Test Compression, Int. Test Conf., 2004. 25
Illinois Scan in CAD Tools
 Cadence (formerly IBM)
 Illinois Scan on their patented “OPMISR” is called
OPMISR+
 Syntest
 Illinois Scan is called “Virtual Scan”
 Synopsis
 ATPG Tools understand and support Illinois Scan
 Mentor Graphics
 No Illinois Scan!
 Proprietary tool called TestCompress

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Illinois Scan with multiple pins
 Large Industrial Circuits have used Illinois Scan
with multiple pins
 IBM ASIC-4 chip (Design and Test, Sept. 2002, pp. 65-72)
 1.14 million gates, 46 pins, 269 internal chains
 Intel chips (Int. Test Conf., Sept. 2003, pp. 1229-1238)
 ASIC-1, 4 pins, 81 internal chains

 ASIC-2, 4 pins, 96 internal chains

 Next generation microprocessor (no data given)

 All of the above scan-chain groupings are ad-hoc!


 Can we do better with intelligent grouping?

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Optimal Grouping of Chains
scan-in scan chains
pins

Objective:
Minimize number of Scan-In Pins without loss in fault coverage.
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Compatibility among Chains
 Compatibility between two scan cells
 Two inputs (scan cells) are compatible if and only if
no fault becomes untestable as a result of tying the
two cells to a single input (Chen&Gupta, ITC 1995)
 Compatibility between two scan chains
 Two chains are compatible if and only if every pair
of scan-cells that receive the same broadcast
value are compatible (Hamzaoglu&Patel, FTCS 1999)
 Determination of all pairwise compatibilities is
computationally very expensive
 Resort to an inexpensive algorithm which gives a
subset of all compatible pairs

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Incompatibilities from a Test Set
A Partially Specified Test Vector, 20-bits long folded on to 5 chains
Vector 1 Chain
001x 0xx1 x01x 0011 xx11 0 0 1 x a
0 x x 1 b
No conflicting values found
x 0 1 x c
0 0 1 1 d
x x 1 1 e
Vector 2
001x 0xx1 x11x 0011 xx11 0 0 1 x a
Chains a and c are incompatible,
0 x x 1 b
so are chains c and d x 1 1 x c
0 0 1 1 d
x x 1 1 e
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Example of Chain Grouping
Given Incompatible Pairs:
AB, AD, AG, BD, BE, BF, CE, CF, EF, EG, EH, FH
Construct a Graph with Nodes=Chains and Edges=Incompatibility

A B C A
B
C

D E F D
E
F
G H G
H

Perform Graph Coloring Algorithm Conflict-free Chain Grouping

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Dual-mode Illinois Scan

A A
B B
C C
D D
E E
F F
G G
H H

Single Pin Broadcast Mode Group Mode

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Dual Mode for Pin Reduction
no. of no. of Reduction
Circuit
Chains Pins Factor
64 8 8.0
s13207.1
107 9 11.8
54 7 7.7
s15850.1
89 11 8.0
52 5 10.4
s38417
82 7 11.7
90 7 12.8
s38584.1
119 8 14.8
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Illinois Scan: Summary
 A simple DFT technique, ideal for reducing test
costs for large chips
 Significant reduction in test application time, test
data and test pins without loss in fault coverage
 Even a “dumb” partition is very effective!
 For large chips, 400 factor reduction is likely!

“Things should be made as simple as possible,


but not any simpler” Albert Einstein

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More information on Illinois Scan
1. I. Hamzaoglu and J.H. Patel, “Reducing test application time for full-scan
embedded cores,” Proc. 29th Int. Symp. On Fault-Tolerant Computing
(FTCS-29), pp.260-267, June 1999
2. F. Hsu, K. Butler and J.H. Patel, “A case study on the implementation of
Illinois Scan Architecture,” Proc. Int. Test Conf. pp. 538-547, October 2001
3. A.R. Pandey and J.H. Patel, “An incremental algorithm for test generation
in Illinois Scan Architecture based designs,” Proc. Of Design Automation and
Test in Europe (DATE), pp. 368-375, March 2002.
4. A.R. Pandey and J.H. Patel, “Reconfiguration techniques for reducing test
time and test data volume in Illinois Scan Architecture based designs,” IEEE
VLSI Test Symp. (VTS), pp. 9-15, April 2002.
5. M.A. Shah and J.H. Patel, “Enhancement of the Illinois Scan Architecture
for Use with Multiple Scan Inputs,” IEEE Computer Society Annual
Symposium on VLSI, pp. 167-172, Feb. 2004. 35