Digital VLSI Design

(ECE314/ ECE514)

Lecture-4

21-Aug-2018
 MOSFET Capacitances 2

CGS CGD

S D

CSB CGB CDB

Anuj Grover
Source: Digital Integrated Circuits, J.Rabbaey,A Chandrakasasn,B Nikolic
 Diffusion Capacitance 3

Channel-stop implant
N A1

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS Substrate N A

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 Wire Resistance 4

R= L
HW

L Sheet Resistance
H Ro

R1 R2
W

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey, A Chandrakasan, B Nikolic
 RC-Models 5

 3-segment p-model
is accurate to 3%
in simulation

 Single segment p-
model commonly
used

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey, A Chandrakasan, B Nikolic
 Crosstalk Effect 6

A B
Cadj
Cgnd Cgnd

• Assume layers above and below on average are quiet

• Second terminal of capacitor can be ignored
• Model as Cgnd = Ctop + Cbot

• Effective Cadj depends on behavior of neighbors

• Miller effect
B DV Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2
Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Devices 7

• MOS Capacitor
• Accumulation
• Depletion
• Inversion – High Frequency/ Low Frequency

• MOS Transistor
• VCCS
• VCR
• Velocity saturation
• Subthreshold operation
• Capacitances

• Interconnects
• Capacitance
• Resistance
• X-talk Anuj Grover
Inverter

Anuj Grover
BJT Inverter 9

Anuj Grover
MOS Inverter 10

Anuj Grover
 CMOS Inverter
N Well VDD

VDD PMOS 2l

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 Two Inverters

Share power and ground

Abut cells
VDD
Connect in Metal

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 DC Response 13

• DC Response: Vout vs. Vin for a gate

• Ex: Inverter
• When Vin = 0 -> Vout = VDD VDD
• When Vin = VDD -> Vout = 0
• In between, Vout depends on
Idsp
• transistor size and current Vin Vout
• By KCL, must settle such that
• Idsn = |Idsp| Idsn
• We could solve equations
• But graphical solution gives more insight

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Transistor Operation 14

• Current depends on region of transistor behavior

• For what Vin and Vout are nMOS and pMOS in

• Cutoff?
• Linear?
• Saturation?

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 nMOS Operation 15

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 I-V Characteristics
• Make pMOS is wider than nMOS such that bn = bp

Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Load Line Analysis
• For a given Vin:
• Plot Idsn, Idsp vs. Vout
• Vout must be where |currents| are equal in

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Load Line Analysis
 Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD

• Vin = 0
V
Vin0 Vin5
V in5
in0

V
Vin1 V
Vin4
dsn, |Idsp
Idsn | in1 in4
dsp

V
Vin2 V
Vin3
in2 in3
V
Vin3 V
Vin2
in3 in2
V
Vin4 V
Vin1
in4 in0
in1
VDD
V
Vout
V
DD
DD
out

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 DC Transfer Curve
• Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Operating Regions
• Revisit transistor operating regions VDD

Vin Vout

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Beta Ratio
• If bp / bn  1, switching point will move from VDD/2

• Called skewed gate

• Other gates: collapse into equivalent inverter

VDD
bp
 10
bn
Vout 2
1
0.5
bp
 0.1
bn

0
VDD
Vin

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Noise Margins
• How much noise can a gate input see before it does not recognize the
input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 25
Logic Levels
• To maximize noise margins, select logic levels at
• unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

b p/b n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Transient Response
• DC analysis tells us Vout if Vin is constant

• Transient analysis tells us Vout(t) if Vin(t) changes

• Requires solving differential equations

• Input is usually considered to be a step or ramp

• From 0 to VDD or vice versa

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Inverter Step Response
• Ex: find step response of inverter driving load cap

Vin (t )  u(t  t0 )VDD

Vin(t)
Vout (t  t0 )  VDD Vout(t)
Cload
dVout (t ) I dsn (t )
 Idsn(t)
dt Cload
Vin(t)

 0 t  t0

I dsn (t )   b
   Vout  VDD  Vt
2
2
VDD V t Vout(t)

 b  VDD  Vt  Vout (t )  V (t ) V  V  V t
 out t0
  2 
out DD t

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Delay Definitions
• tpdr: rising propagation delay
• From input to rising output
crossing VDD/2

• tpdf: falling propagation delay

• From input to falling output
crossing VDD/2

• tpd: average propagation delay

• tpd = (tpdr + tpdf)/2

• tr: rise time

• From output crossing 0.2 VDD
to 0.8 VDD

• tf: fall time

• From output crossing 0.8 VDD
to 0.2 VDD
Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Delay Definitions
• tcdr: rising contamination delay
• From input to rising output crossing VDD/2

• tcdf: falling contamination delay

• From input to falling output crossing VDD/2

• tcd: average contamination delay

• tpd = (tcdr + tcdf)/2

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris