RISC | Instruction Set | 64 Bit Computing

UNIT - I

CHAPTER ± 1

RISC
REDUCED INSTRUCTION SET COMPUTER

RISC - Machines
(1) UltraSPARC Architecture (2) PowerPC Architecture (3) Cray T3E Architecture

Some architecture that support RISC architecture is as follow: * UltraSPARC architecture * PowerPC architecture * Cray T3E architecture . single cycle execution of instruction.memory access is done by ¶Load & storeµ instruction. fixed instruction length.‡ Introduction .characterization of RISC standard.RISC was developed in early 1980·s. The purpose of RISC is ´simplify the design processors·. . .

‡ Other member of SPARC family is variety of SPACR processor.(1) UltraSPARC Architecture ‡ UltraSPARC processor was introduced by Sun Microsystems in 1995 ‡ It·s the latest member of SPARC family. superSPARC processor ‡ The original SPARC architecture was developed in mid-1980·s ‡ SPARC ² standard for Scalable Processor Architecture ‡ UltraSPACR ² suitable for Micro ² computers Super-computers because implementations are carried in wide range .

formation of word No.(1) Memory .UltraSPARC programs are written using Virtual Address Space of of 2 64 bytes -address space Divided into pages Some of the pages are stored in disk physical memory . of consecutive bytes 2 4 8 formation Halfword Word doubleword .memory consist of 8-bit bytes .address use byte addresses .

* Condition code register . but original SPACR architecture is 32-bit in long.‡ Virtual address specified Automatically translated physical address By using instruction (2) Register UltraSPARC (MMU) * SPARC ² contains 100-general purpose register. * UltraSPARC architecture contains 64-bits in long. * Program Counter register (PC) it contains the address of next register next instruction going to be executed. * Floating point registers UltraSPARC architecture contain 64-double preceision floating point registers.

& ³little-endian´ 2 Floating point ‡ stored in 3-different format 1. sign of floating point(1-bit) 3.exponent(8-bit).No 1 Data Type Integer Store As ‡UltraSPARC ‡ both signed & undsinged integers are supported ‡ integers are sotred as 8.(3) Data Foramt S. Double precision format (64-bit) Floating point(52-bit). * ultraSPACR support both ³big-endian´. quad-precision it stores 63-significant bits 15 bits for exponent Character 8-bit ASCII 3 .exponent(11-bit). single precision format (32-bit) Floating pint (23-bit). sign of floating point (1-bit) 2. 32 /64 bit binary number ‡Original SPARC ‡ Big endian the most significant part of numeric value is stored at lowest numbered address is called ³big-endian´. 16.

that enters value into a register 32-bit Format-3 * used for Load & Store registers * and three arithmetic operand operations .(4) Instruction format Format-1 * used for call instruction 32-bit Instruction Three basic Instruction format Format 32-bit Format-2 * used for Branch instruction * one special instruction.

signed} TA= (Register-1) + (register-2) (6) Instruction set * The SPARC architecture has more than 100-machine instruction * Load & store registers (only one instruction) . signed} TA = (register) + displacement { 13-bits.used to access memory * other instructions are used to perform register-to-register operation.No. * instruction execution on SPARC system ³pipelined´. which means while one instruction is being executed the next instruction is fetched by memory.(5) Addressing modes S. 1 2 3 Modes PC-relative Register indirect with displacement Register indirect indexed Target Address calculation TA = (PC) + displacement { 30-bits. .

11.g) SUB %Lo. (7) Input & Output .the MOV ± instruction is called ³delay state´.* To make the pipeline to work more efficiently.the MOV-instruction is executed before the branch BA. %L1 BA NEXT MOV %L1.each I/O put device communication is carried out by memory . .each I/O device has unique address (or) set of address . %03 . branch instruction are treated as ³delayed branches´. (e.

PowerPC Architecture .

600. Apple. * The acronym of POWER is Performance Optimization With Enhanced RISC * In October-1991 IBM.‡ Introduction * In 1990. Motorola formed an alliance to develop & market powerful & low-cost microprocessor. * In In 1993 the first product of PwoerPC chips were delivered. 603. the IBM first introduced the PowerPC architecture with Rs. 604 * Further information about PowerPC can be found in 1994. . The implementation of powerPC architecture are PowerPC-601.

and address are byte address * Formation of word No.(1) Memory * Memory consist of 8-bit byte. of consecutive bytes 2 4 8 16 formation Halfword Word Doubleword quadword * PowerPC programs can be written using a virtual address space of 2 64 bytes. * virtual address space segment Divided into (256-MB) Divided into pages (4096-bytes) some of the pages used by physical memory some of the pages used are stored in disk .

contains 64-bit long registers. .(2) Registers (a) General purpose registers .32 bit condition registers .designated from GPR0 t0 GPR31 .full powerPC architecture.it·s used as mechanism of testing & branching instruction . & status register & control registers. .32-general purpose registers .used for some branch instruction (e) Machine status Register (MSR) .powerPC architecture also implemented on 32-bit registers .it contain 32-bit floating point register.this register is divided into eight 4-bit subfields CR0 to CR7 (d) Link Register & Count Register .computation of floating point is carried out by special FPU. (c) Condition register .this register is depend on implementaion .usage: store & manipulate integer data & address (b) Floating Point registers (FPU) .

sign of FP(1-bit) * Double precision (63-bit) Floating point(52-bit). (bigendian byte ordering).exponent value(11-bit).32/64 bit binary number ‡Both signed & unsigned integers are stored ‡-tive values are stored as 2·s complement ‡Most significant part of numeric value is stored at ´lowest numbered addressµ. ‡Two different floating point format * single precision format (32-bit) Floating point(23-bit).exponent value(8-bit).(3) Data formats S.No Data Types Stored as 1 Integers ‡8.sign of FP(1-bit) ‡8-bit ASCII code 2 Floating Point 3 Character .16.

there are 7 basic instruction formats.(4) Instruction format 1. instruction must be aligned at the beginning of word boundary 4. the first 6-bit of instruction word specify opcode. 5. some instruction may have extended opcode field. 2.No. Some of the instruction formats have sub format. 1 2 3 Modes Immediate addressing mode Register direct addressing mode Load & store operation & Branch instruction An operand value may be specified as a part of the instruction itself An operand value may be specified as a part of the register itself This is the only instruction address the memory . (5) Addressing Modes S. All of these instruction are 32-bit long 3.

No.No. signed} ‡ Branch instruction use any one of the following addressing mode S. 1 2 3 4 Absolute Relative Link Register Count Register Mode Target Address Calculation TA=actual address TA=current instruction address + disp {25 bits.‡ Load & store operation use any one of the following addressing mode S. 1 2 3 Mode Register indirect Register indirect with index Register indirect with immediate index Target Address Calculation TA=(register) TA=(register-1)+(register-2) TA=(register) + disp {16-bit. signed} TA=(LR) TA=(CR) .

* instruction execution on PowerPC is ´Pipelineµ. * floating point addition & multiplication instruction take 3-i/p operand to perform multiplication & addition in one instruction. .g) * Load & store instruction automatically update the index register to compute TA. branch prediction is used speed the execution of instruction * delayed brnach instruction is not used in powerPC architect. (7) Input & Output * This architect provide 2 different method to perform I/O operations (1) Direct storage segments Segments in virtual address space are mapped onto an external address space (2) Indirect storage segment I/O is performed using regular virtual memory management H/W & S/W.(6) Instruction Set * It contains approximately 200-machine instructions * some instructions are more complex (e.

CRAY T3E ARCHITECTURE .

‡ Introduction * in 1995. the T3E supercomputers was developed by ´Cray researchµ * T3E supports: Massively Parallel Processing (MPP) (any machine having 100 (or) 1000 of processors is called MPP) * Reason for supporting used for technical applications in scientific computing * T3E-contains large number of processing elements. arranged in 3D-network overall T3E architecture Interconnect network Processing element node .

control logic (1) Memory * each PE in 3E has from 64-MB to 2-GB capacity of local memory * Local memory in PE is .Logically shared memory system because PE-1 microprocessor access PE-2 memory Without involving microprocessor of PE-2 . local memory.physically distributed because each PE contains local memory . * In each dimension.* The 3D.n/w provides a path for transferring data between processors. * T3E-system contains from 16 to 2048 processing elements * Each processing element contains DEC Alpha EV5 RISC ² microprocessor. the inter-connect n/w is circular.

of consecutive bytes 2 4 8 (2) Registers formation word Long word Doubleword * Alpha architecture contains -32 general purpose registers (R0 to R31) -each general purpose register is 64-bit long -uses· of general purpose register state & manipulate integer data & addresses.* each processing element memory consist of 8-bit bytes * addresses used are byte address * word formation No. .

1 2 3 Integer Negative values Floating-point (two groups) Data types Stored as Longword (or) quadword 2·s complement ‡First group 3-formats with compatibility of VAX ‡Second group 4-formats with IEEE-std compatibility of modern systems.No.each floating point register is 64-bit long * Program counter register (64-bit) * Status & control register (3) Data formats S.* Floating point registers . ‡8-bit ASCII code 4 Characters .32 floating point registers (F0 to F31) .

No. 1 2 Modes Immediate addressing mode Register direct addressing mode An operand value may be specified as a part of the instruction itself An operand value may be specified as a part of the register itself . some instruction format have additional function field (5) Addressing modes S.(4) Instruction formats * five basic instruction formats with 32-bit long * the first 6-bit of instruction format specify the ´opcodeµ.

then the implementation of this architecture is fast.* operand in memory are addressed using one of following mode S. signed} Use Condition & unconditional branches Load & store operation & Subroutine jumps 2 Register indirect with displacement TA=(register-1)+ disp {16-bit. * If the instruction set is designed well. .signed} (6) Instruction set * The Alpha architecture contain 130 machine instructions (it reflect RISC orientation). 1 Mode PC relative Target Address Calculation TA=(PC) + disp {23 bits.No.

* Every 8-Processing Elements contains one I/O channel. .(7) Input & Output * I/p & O/p performed using I/O channels.

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